DLP29007-2015-1

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1 EngTel: Programmable Logic Devices II - 2015-1

  • Lecturers: Arliones Hoeller e Marcos Moecke
  • Class: 29007
  • Meetings: tuesdays at 9:40 and thursdays at 7:30 at Laboratório de Programação.
  • Extra-class hours:
    • Arliones: tuesdays from 13:30 until 15:20
    • Marcos:

1.1 Course Plan (in Portuguese)

1.2 Class Schedule

1.3 Grades

Registration T0 T1 T2 T3 T4 T5 Final

2 Class Material

2.1 Bibliographic References

  1. Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN 0471720925.
  2. David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, Burlington, 2007, Pages 3-48, ISBN 9780123704979, http://dx.doi.org/10.1016/B978-012370497-9/50002-0.

2.2 Lecture Notes

These lecture notes are based on the ones made available by Prof. Pong P. Chu at [1].


2.3 Recursos de Laboratório

Para uso fora do IFSC dos recursos computacionais com licença educacional, o IFSC disponibiliza para seus alunos o IFSC-CLOUD. Atualmente a forma mais eficiente de acesso é através do Cliente X2GO. O procedimento de instalação/ configuração e uso do Quartus/Modelsim/QSIM está descrito em Acesso ao IFSC-CLOUD#Cliente X2GO (recomendado).

Para a geração de documentação/relatórios técnicos/artigos, está disponibilizada a plataforma Sharelatex do IFSC-CLOUD. Utilize preferencialmente o modelo de artigo no padrão ABNT.

2.4 Homework

Homework Deadline
Homework 1: Operator Sharing 19/02
Homework 2: Function Sharing 26/02
Homework 3: Combinational Circuits 03/03
Homework 4: Derived Clocks 23/03
Homework 5: Sequential Circuits 23/03

3 Class log

3.1 05/02: Course presentation. Complexity Management. Overview of Complex Digital Systems Desgin.

3.1.1 Recommended reading

  • Chapter 1 of bibliographic references 1 AND 2.
  • Lecture notes 1.


3.2 12/02 - 26/02: Design of efficient combinational circuits

3.2.1 Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.
  • TimeQuest Help, mainly Propagation Delay Report.

3.3 12/02: Design of efficient combinational circuits: Operator sharing

3.3.1 Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


3.3.2 Homework 1

Combinational Circuits (Prazo de entrega 19/02/2015)

Download the Operator Sharing Source Code (qar) or Operator Sharing Source Code (qar.zip) and, for each architecture of each one of the three examples, do the following:

  • Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
  • Select the "Fastest" "Speed grade";
  • Select the smallest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
  • Change to the largest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;

Write a report containing the numeric results of your experiments. For each example, answer the following questions:

  1. Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
  2. Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?

Email the results to the professors until 17/02/2015.

3.4 19/02: Design of efficient combinational circuits: Function sharing

3.4.1 Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


3.4.2 Homework 2

Combinational Circuits (Prazo de entrega 26/02/2015)

Download the Function Sharing Source Code (qar.zip) and, for each architecture of each one of the examples, do the following:

  • Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
  • Select the "Fastest" "Speed grade";
  • Select the smallest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
  • Change to the largest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;

Write a report containing the numeric results of your experiments. For each example, answer the following questions:

  1. Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
  2. Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?

Email the results to the professors until next class.

3.5 26/02: Design of efficient combinational circuits: Layout Considerations

3.5.1 Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


3.5.2 Homework 3

Combinational Circuits (Prazo de entrega 03/03/2015)

Groups of two students will study and explain to the class one of these circuits in Chapter 7 of bibliographic reference 1: 7.5.2 (Programmable Priority Encoder), 7.5.4 (Combinational Adder-Based Multiplier), 7.5.5 (Hamming Distance Circuit).

3.6 03/03: Design of efficient combinational circuits: General Circuits

Students presented and discussed the general circuits of section 7.5 of bibliographic reference 1.

3.6.1 Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.

3.7 06/03: Design of efficient sequential circuits: principle

3.7.1 Recommended reading

  • Chapter 8 of bibliographic reference 1.
  • Lecture note 3.

3.8 12/03 and 17/03: Design of efficient sequential circuits: principle and practice

3.8.1 Recommended reading

  • Chapter 8 of bibliographic reference 1.
  • Chapter 9 of bibliographic reference 1.
  • Lecture notes 3.
  • Lecture notes 4.
  • Quartus II help - create_clock - ALTERA

3.8.2 Homework 4

Projeto sincrono - Timer (HORA, MINUTO, SEGUNDO) - (Prazo de entrega 23/03/2015)
  • Grupos de 2 alunos!
  • Implementar um timer que tenha saída de segundo, minuto e hora (todos em binário).
  • Versão 1: Utilizando clocks derivados de 1seg, 1min a partir de 50 MHz.
  • Versão 2: Projeto Síncrono com clock global.
  • Simular o timer (versão 1 e 2), mostrando o correto funcionamento.
  • Análisar o RTL e número de elementos necessários.
  • Criar um arquivo timer.sdc e incluí-lo no projeto (para definir a restrição de tempo do clock máximo)
create_clock -name CLK50MHz -period 20 [get_ports {clk}]

ou 

create_clock -name CLK50MHz -period 250MHz [get_ports {clk}]
  • Verificar no {Compilation Report > TimeQuest Timing Analyser}, se o clock máximo do circuito obtido é maior que 50 MHz.
  • ATENÇÃO AINDA NÃO ESTÁ FECHADO O PROJETO.


3.8.3 Homework 5

Sequential Circuits (Prazo de entrega 23/03/2015)

Each student will synthesize and analyze a counter, according to the list bellow.

  • Danilo: Binary Counter
  • Elton: Decimal Counter
  • Ernani: Gray Counter
  • Jean: Johnson Counter
  • Leonan: LFSR Counter
  • Thiago Henrique: PWM Counter
  • Thiago Werner: Ring Counter

Students must:

  1. Report area of the design
  2. Report maximum delays and clock of the design using the SDC file to set up a target clock
  3. Modify circuits to increase maximum frequency in a Cyclone
  4. Try to synthesize the counter at 300MHz in any other FPGA
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