DLP29007-2015-1

De MediaWiki do Campus São José
Ir para: navegação, pesquisa

EngTel: Programmable Logic Devices II - 2015-1

  • Lecturers: Arliones Hoeller e Marcos Moecke
  • Class: 29007
  • Meetings: tuesdays at 9:40 and thursdays at 7:30 at Laboratório de Programação.
  • Extra-class hours:
    • Arliones
      • Tuesdays, 14:30 to 15:30
      • Thursdays, 10:30 to 11:30
    • Marcos
      • Tuesdays, 13:30 to 14:30
      • Thursdays, 10:30 to 11:30

Course Plan (in Portuguese)

Class Schedule

Grades

Registration T0 T1 T2 T3 T4 T5 Final

Class Material

Bibliographic References

  1. Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN 0471720925.
  2. David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, Burlington, 2007, Pages 3-48, ISBN 9780123704979, http://dx.doi.org/10.1016/B978-012370497-9/50002-0.

Lecture Notes

These lecture notes are based on the ones made available by Prof. Pong P. Chu at [1].

  • [ Lecture 09: Parameterized Design: Principle]
  • [ Lecture 10: Parameterized Design: Practice]
  • [ Lecture 11: Clock and Synchronization: Principle and Practice]


Recursos de Laboratório

Para uso fora do IFSC dos recursos computacionais com licença educacional, o IFSC disponibiliza para seus alunos o IFSC-CLOUD. Atualmente a forma mais eficiente de acesso é através do Cliente X2GO. O procedimento de instalação/ configuração e uso do Quartus/Modelsim/QSIM está descrito em Acesso ao IFSC-CLOUD#Cliente X2GO (recomendado).

Para a geração de documentação/relatórios técnicos/artigos, está disponibilizada a plataforma Sharelatex do IFSC-CLOUD. Utilize preferencialmente o modelo de artigo no padrão ABNT.

Homework

Homework 01: Combinational Circuits (Deadline: 19/02/2015)

Download the Operator Sharing Source Code (qar) or Operator Sharing Source Code (qar.zip) and, for each architecture of each one of the three examples, do the following:

  • Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
  • Select the "Fastest" "Speed grade";
  • Select the smallest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
  • Change to the largest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;

Write a report containing the numeric results of your experiments. For each example, answer the following questions:

  1. Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
  2. Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?

Email the results to the professors until 17/02/2015.

Homework 02: Combinational Circuits (Deadline 26/02/2015)

Download the Function Sharing Source Code (qar.zip) and, for each architecture of each one of the examples, do the following:

  • Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
  • Select the "Fastest" "Speed grade";
  • Select the smallest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
  • Change to the largest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;

Write a report containing the numeric results of your experiments. For each example, answer the following questions:

  1. Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
  2. Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?

Email the results to the professors until next class.

Homework 03: Combinational Circuits (Deadline: 03/03/2015)

Groups of two students will study and explain to the class one of these circuits in Chapter 7 of bibliographic reference 1: 7.5.2 (Programmable Priority Encoder), 7.5.4 (Combinational Adder-Based Multiplier), 7.5.5 (Hamming Distance Circuit).

Homework 04: Synchronous Project - Timer (hour, minute, second) - (Deadline: 24/03/2015)
  • Groups of 2 students!
  • Implement a timer with outputs seconds, minutes and hour (in binary mode);
  • Version 1: Use derived clocks of 1 second, 1 minute, and 1 hour, all from a 50 MHz source.
  • Version 2: Build a synchronous desing using a global clock.
  • Simulate the timer (both versions), showing the correct behaviour.
  • Analyse the RTL and report the number of logic elements used.
  • Create a timer.sdc file and include it in the project (to define a clock restriction)
create_clock -name CLK50MHz -period 20 [get_ports {clk}]

OR

create_clock -name CLK50MHz -period 250MHz [get_ports {clk}]
  • Check at {Compilation Report > TimeQuest Timing Analyser} if the maximum clock of the circuit is greater than 50 MHz.
Homework 05: Sequential Circuits (Deadline: 26/03/2015)

Each student will synthesize and analyze a counter, according to the list bellow.

  • Danilo: Binary Counter
  • Elton: Decimal Counter
  • Ernani: Gray Counter
  • Jean: Johnson Counter
  • Leonan: LFSR Counter
  • Thiago Henrique: PWM Counter
  • Thiago Werner: Ring Counter

Students must:

  1. Use synchronous design methodology, with separate segment for memory, next-state logic and output logic;
  2. Use a GENERIC constant to define the counter size, and test the counter for 3 and 8 bits.
  3. Simulate the counter (and variations), showing the correct behaviour.
  4. Analyze the RTL and report the number of logic elements used. Observe that the clock is global and without interruptions by ports.
  5. Create a counter.sdc file and include it in the project (to define a clock restriction)
create_clock -name CLK250MHz -period 250MHz [get_ports {clk}]
  1. Report area of the design (and variations);
  2. Report maximum delays and clock of the design using the SDC file to set up a target clock;
  3. Modify circuits to increase maximum frequency in a Cyclone;
  4. Try to synthesize the counter at 250MHz in any other FPGA.
Homework 06: Finite State Mahines with Datapath (Deadline: 19/05/2015)

In this homework you must produce a report in the format of an article. The article template can be downloaded here. The report will describe a lab experiment including the exercises from the Pong Chu book, enumerated bellow. You must simulate your designs to show that they work properly, and report differences in area and maximum clock among different designs. Don't forget to include the FSM/FSMD and/or ASM/ASMD in the report. When modifying a design shown in the book, compare the results with the original design.

Exercises:

  • Group 1 (names here): 10.3, 10.4, 11.6
  • Group 2 Elton e Thiago Henrique: 10.8, 11.7
  • Group 3 Leonan e Thiago Werner: 10.10, 11.5

Class log

05/02: Course presentation. Complexity Management. Overview of Complex Digital Systems Desgin.

Recommended reading

  • Chapter 1 of bibliographic references 1 AND 2.
  • Lecture notes 1.


12/02 - 26/02: Design of efficient combinational circuits

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.
  • TimeQuest Help, mainly Propagation Delay Report.

12/02: Design of efficient combinational circuits: Operator sharing

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


19/02: Design of efficient combinational circuits: Function sharing

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


26/02: Design of efficient combinational circuits: Layout Considerations

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


03/03: Design of efficient combinational circuits: General Circuits

Students presented and discussed the general circuits of section 7.5 of bibliographic reference 1.

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.

05/03: Design of efficient sequential circuits: principle

Recommended reading

  • Chapter 8 of bibliographic reference 1.
  • Lecture note 3.

12/03, 17/03, 26/03 and 31/03: Design of efficient sequential circuits: principle and practice

Recommended reading

  • Chapter 8 of bibliographic reference 1.
  • Chapter 9 of bibliographic reference 1.
  • Lecture notes 3.
  • Lecture notes 4.
  • Quartus II help - create_clock - ALTERA


07/04, 09/04 and 16/04: Design of Efficient Finite State Machines: principle and practice

Recommended reading

  • Chapter 10 of bibliographic reference 1.
  • Lecture notes 5.

23/04: Register Transfer Methodology: Principle

Recommended reading

  • Chapter 11 of bibliographic reference 1.
  • Lecture notes 6.


11/06: Embedded Processors (SoC)

In this class we will follow an Altera tutorial to build a System-on-a-Chip (SoC), synthesizing a NIOS processor softcore in a FPGA and loading an OS on it. Later on we will integrate our own logic with this processor.

The guidelines to this tutorial are on this page.

You will need these additional components:


If the Eclipse SBT for Nios II does not start in your Ubuntu 14.04 system, you may need to install libGTK2:

sudo apt-get install libgtk2.0-0:i386

23/06: Final Project

Overview

ProcessadorDeAudioSeguro.png

In this project you'll implement a secure audio transceiver using Macnica's Mercurio IV platform with an Cyclone IV E FPGA. A general overview is presented in the figure above, which is comprised of these blocks:

  • Inputs
    • in ADC: the ADC chip avaliable in the board. It is connected to the FPGA through an SPI interface, delivering a 12-bit decimal value.
    • in Shared Key: a 128-bit shared key for the AES block cipher.
    • out DAC: the DAC chip avaliable in the board. It is connected to the FPGA through an SPI interface, receiving a 12-bit decimal value.
  • Processing blocks
    • Nios II: The Nios II will act as SPI master to read data from the ADC and write data to the DAC. The software in the CPU will read data from the ADC at a 8KHz rate and insert the 12-bit values in an 8-position, 32-bit output FIFO. It will also read data from the input FIFO at an 8KHz rate and write it to the DAC. Note: you will only use the 12 LSB of FIFOs' entries.
    • Lei A: the LeiA block of the sending segment will read each 12-bit entry from the FIFO and generate a compressed 8-bit output. In the receive segment, the LeiA block will receive 8-bit values from the AES block and expand them to 12-bit values.
    • AES: The data will be encrypted using an AES-128 algorithm. In the transmission segment, the AES block will need to receive successive 8-bit results from the LeiA block and assembly a 128-bit block to input the cipher. In the receive segment, the AES block will receive successive 8-bit data from the UART block to assembly a 128-bit block to input to the decrypt algorithm.
    • UART: data transmission will be performed through an UART interface connected to an RS-232 transceiver in the board. The UART receiver and transmitter must be extended from the UART receiver studied in class to include the transceiver and the RTS and CTS signals.


  • The following files are avaliable to integrate to your project:
    • Download here a QAR File containing the ADC and DAC adaptation circuit and a Nios2 processor. From this file, you will use a the ADC_OUT FIFO as a data source to your LawA compressor, and the DAC_IN FIFO as a data destination for your LawA decompressor.
    • Download here the ecliplse project of the application that should run on the Nios2 processor. You will need to generate the BSP (sopcinfo file is in the QAR).

Material de apoio para o projeto

  • Conversores Analógico-Digital (CAD) e Conversor Digital-Analógico (CDA)
Ver: Moecke, M. Curso de Telefonia Digital, ETFSC, 1998
  • Implementação de um codificador/decodificador para Lei A.

Compressão e descompressão pela Lei A

FONTE: Moecke, M. Curso de Telefonia Digital, ETFSC, 1998, ITU-T, Recommendation G.711 (11/88)

25/06: Final Project

  • Implementation of VHDL description of an AES 128 cypher operating with 128-bit keys and 128-bit data blocks.
    • See this article for the description of the algorithm;
    • Read printed book segment handed on to you in class.
    • Check out these software implementations that may help you with the Register Transfer Methodology to implement AES. The software in Python is a high-level implementation (easy to understand). The C++ implementations are Object-Oriented and easy to integrate in software projects, but their code show several tweaks to make it faster in x86 machines with ssse3 instructions, or certain DSP devices (only recommended for those with a strong heart).


AES128 overview.png