Mudanças entre as edições de "DLP29007-2015-1"
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* [http://www.macnicadhw.com.br/c/document_library/get_file?uuid=0612db45-0434-4737-a380-ac846cf662b3&groupId=10157 MercurioIV schematic] | * [http://www.macnicadhw.com.br/c/document_library/get_file?uuid=0612db45-0434-4737-a380-ac846cf662b3&groupId=10157 MercurioIV schematic] | ||
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+ | If the Eclipse SBT for Nios II does not start in your Ubuntu 14.04 system, you may need to install libGTK2: | ||
+ | sudo apt-get install libgtk2.0-0:i386 |
Edição das 11h21min de 17 de junho de 2015
EngTel: Programmable Logic Devices II - 2015-1
- Lecturers: Arliones Hoeller e Marcos Moecke
- Class: 29007
- Meetings: tuesdays at 9:40 and thursdays at 7:30 at Laboratório de Programação.
- Extra-class hours:
- Arliones
- Tuesdays, 14:30 to 15:30
- Thursdays, 10:30 to 11:30
- Marcos
- Tuesdays, 13:30 to 14:30
- Thursdays, 10:30 to 11:30
- Arliones
Course Plan (in Portuguese)
Class Schedule
Grades
Registration | T0 | T1 | T2 | T3 | T4 | T5 | Final |
---|---|---|---|---|---|---|---|
Class Material
Bibliographic References
- Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN 0471720925.
- David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, Burlington, 2007, Pages 3-48, ISBN 9780123704979, http://dx.doi.org/10.1016/B978-012370497-9/50002-0.
Lecture Notes
These lecture notes are based on the ones made available by Prof. Pong P. Chu at [1].
- Lecture 01: Complexity Mangement and the Design of Complex Digital Systems
- Lecture 02: Efficient Design of Combinational Circuits
- Lecture 03: Efficient Design of Sequential Circuits
- Lecture 04: Design of Sequential Circuits: Practice
- Lecture 05: Finite State Machines: Principle and Practice
- Lecture 06: Register Transfer Methodology: Principle
- Lecture 07: Register Transfer Methodology: Practice
- Lecture 08: Hierarchical Design
- [ Lecture 09: Parameterized Design: Principle]
- [ Lecture 10: Parameterized Design: Practice]
- [ Lecture 11: Clock and Synchronization: Principle and Practice]
Recursos de Laboratório
Para uso fora do IFSC dos recursos computacionais com licença educacional, o IFSC disponibiliza para seus alunos o IFSC-CLOUD. Atualmente a forma mais eficiente de acesso é através do Cliente X2GO. O procedimento de instalação/ configuração e uso do Quartus/Modelsim/QSIM está descrito em Acesso ao IFSC-CLOUD#Cliente X2GO (recomendado).
Para a geração de documentação/relatórios técnicos/artigos, está disponibilizada a plataforma Sharelatex do IFSC-CLOUD. Utilize preferencialmente o modelo de artigo no padrão ABNT.
Homework
Homework 01: Combinational Circuits (Deadline: 19/02/2015) |
---|
Download the Operator Sharing Source Code (qar) or Operator Sharing Source Code (qar.zip) and, for each architecture of each one of the three examples, do the following:
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
Email the results to the professors until 17/02/2015. |
Homework 02: Combinational Circuits (Deadline 26/02/2015) |
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Download the Function Sharing Source Code (qar.zip) and, for each architecture of each one of the examples, do the following:
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
Email the results to the professors until next class. |
Homework 03: Combinational Circuits (Deadline: 03/03/2015) |
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Groups of two students will study and explain to the class one of these circuits in Chapter 7 of bibliographic reference 1: 7.5.2 (Programmable Priority Encoder), 7.5.4 (Combinational Adder-Based Multiplier), 7.5.5 (Hamming Distance Circuit). |
Homework 04: Synchronous Project - Timer (hour, minute, second) - (Deadline: 24/03/2015) |
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create_clock -name CLK50MHz -period 20 [get_ports {clk}] OR create_clock -name CLK50MHz -period 250MHz [get_ports {clk}]
|
Homework 05: Sequential Circuits (Deadline: 26/03/2015) |
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Each student will synthesize and analyze a counter, according to the list bellow.
Students must:
create_clock -name CLK250MHz -period 250MHz [get_ports {clk}]
|
Homework 06: Finite State Mahines with Datapath (Deadline: 19/05/2015) |
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In this homework you must produce a report in the format of an article. The article template can be downloaded here. The report will describe a lab experiment including the exercises from the Pong Chu book, enumerated bellow. You must simulate your designs to show that they work properly, and report differences in area and maximum clock among different designs. Don't forget to include the FSM/FSMD and/or ASM/ASMD in the report. When modifying a design shown in the book, compare the results with the original design. Exercises:
|
Class log
05/02: Course presentation. Complexity Management. Overview of Complex Digital Systems Desgin.
Recommended reading
- Chapter 1 of bibliographic references 1 AND 2.
- Lecture notes 1.
12/02 - 26/02: Design of efficient combinational circuits
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
- TimeQuest Help, mainly Propagation Delay Report.
12/02: Design of efficient combinational circuits: Operator sharing
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
19/02: Design of efficient combinational circuits: Function sharing
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
26/02: Design of efficient combinational circuits: Layout Considerations
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
03/03: Design of efficient combinational circuits: General Circuits
Students presented and discussed the general circuits of section 7.5 of bibliographic reference 1.
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
06/03: Design of efficient sequential circuits: principle
Recommended reading
- Chapter 8 of bibliographic reference 1.
- Lecture note 3.
12/03, 17/03, 26/03 and 31/03: Design of efficient sequential circuits: principle and practice
Recommended reading
- Chapter 8 of bibliographic reference 1.
- Chapter 9 of bibliographic reference 1.
- Lecture notes 3.
- Lecture notes 4.
- Quartus II help - create_clock - ALTERA
07/04, 10/04 and 17/04: Design of Efficient Finite State Machines: principle and practice
Recommended reading
- Chapter 10 of bibliographic reference 1.
- Lecture notes 5.
23/04: Register Transfer Methodology: Principle
Recommended reading
- Chapter 11 of bibliographic reference 1.
- Lecture notes 6.
11/06: Embedded Processors (SoC)
In this class we will follow an Altera tutorial to build a System-on-a-Chip (SoC), synthesizing a NIOS processor softcore in a FPGA and loading an OS on it. Later on we will integrate our own logic with this processor.
The guidelines to this tutorial are on this page.
You will need these additional components:
If the Eclipse SBT for Nios II does not start in your Ubuntu 14.04 system, you may need to install libGTK2:
sudo apt-get install libgtk2.0-0:i386