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== Homework ==
 
== Homework ==
  
−
{| class="wikitable"
+
{{collapse top| Homework 01: Combinational Circuits (Deadline: 19/02/2015)}}
−
|-
+
Download the [[Media:dlp29007-Unidade2_Ex1-2-4.qar | Operator Sharing Source Code (qar)]] or [[Media:dlp29007-lecture02-efficient_comb_circuits-operator_sharing-src.zip | Operator Sharing Source Code (qar.zip)]] and, for each architecture of each one of the three examples, do the following:
−
!Homework
+
* Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
−
!Deadline
+
* Select the "Fastest" "Speed grade";
−
|-
+
* Select the smallest device available in the family;
−
|[[DLP29007-2015-1#Homework_1 | Homework 1: Operator Sharing]]
+
* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
−
|19/02
+
* Change to the largest device available in the family;
−
|-
+
* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
−
|[[DLP29007-2015-1#Homework_2 | Homework 2: Function Sharing]]
+
 
−
|26/02
+
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
−
|-
+
#Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
−
|[[DLP29007-2015-1#Homework_3 | Homework 3: Combinational Circuits]]
+
#Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?
−
|03/03
+
 
−
|-
+
Email the results to the professors until 17/02/2015.
−
|[[DLP29007-2015-1#Homework_4 | Homework 4: Derived Clocks]]
+
{{collapse bottom}}
−
|24/03
+
 
−
|-
+
{{collapse top| Homework 02: Combinational Circuits (Deadline 26/02/2015)}}
−
|[[DLP29007-2015-1#Homework_5 | Homework 5: Sequential Circuits]]
+
Download the [[Media:dlp29007-lecture02-efficient_comb_circuits-function_sharing-src.zip | Function Sharing Source Code (qar.zip)]] and, for each architecture of each one of the examples, do the following:
−
|26/03
+
* Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
−
|}
+
* Select the "Fastest" "Speed grade";
 +
* Select the smallest device available in the family;
 +
* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
 +
* Change to the largest device available in the family;
 +
* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
 +
 
 +
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
 +
#Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
 +
#Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?
 +
 
 +
Email the results to the professors until next class.
 +
{{collapse bottom}}
 +
 
 +
{{collapse top| Homework 03: Combinational Circuits (Deadline: 03/03/2015)}}
 +
Groups of two students will study and explain to the class one of these circuits in Chapter 7 of bibliographic reference 1: 7.5.2 (Programmable Priority Encoder), 7.5.4 (Combinational Adder-Based Multiplier), 7.5.5 (Hamming Distance Circuit).
 +
{{collapse bottom}}
 +
 
 +
{{collapse top| Homework 04: Synchronous Project - Timer (hour, minute, second) - (Deadline: 24/03/2015)}}
 +
* '''Groups of 2 students!'''
 +
* Implement a timer with outputs seconds, minutes and hour (in binary mode);
 +
* Version 1: Use derived clocks of 1 second, 1 minute, and 1 hour, all from a 50 MHz source.
 +
* Version 2: Build a synchronous desing using a global clock.
 +
* Simulate the timer (both versions), showing the correct behaviour.
 +
* Analyse the RTL and report the number of logic elements used.
 +
* Create a '''timer.sdc''' file and include it in the project (to define a clock restriction)
 +
create_clock -name CLK50MHz -period 20 [get_ports {clk}]
 +
OR
 +
create_clock -name CLK50MHz -period 250MHz [get_ports {clk}]
 +
* Check at '''{Compilation Report > TimeQuest Timing Analyser}''' if the maximum clock of the circuit is greater than 50 MHz.
 +
{{collapse bottom}}
 +
 
 +
{{collapse top| Homework 05: Sequential Circuits (Deadline: 26/03/2015)}}
 +
Each student will synthesize and analyze a counter, according to the list bellow. 
 +
*Danilo: Binary Counter
 +
*Elton: Decimal Counter
 +
*Ernani: Gray Counter
 +
*Jean: Johnson Counter
 +
*Leonan: LFSR Counter
 +
*Thiago Henrique: PWM Counter
 +
*Thiago Werner: Ring Counter
 +
 
 +
Students must:
 +
# Use synchronous design methodology, with separate segment for memory, next-state logic and output logic;
 +
# Use a GENERIC constant to define the counter size, and test the counter for 3 and 8 bits.
 +
# Simulate the counter (and variations), showing the correct behaviour.
 +
# Analyze the RTL and report the number of logic elements used. Observe that the clock is global and without interruptions by ports.
 +
# Create a '''counter.sdc''' file and include it in the project (to define a clock restriction)
 +
create_clock -name CLK250MHz -period 250MHz [get_ports {clk}]
 +
# Report area of the design (and variations);
 +
# Report maximum delays and clock of the design using the SDC file to set up a target clock;
 +
# Modify circuits to increase maximum frequency in a Cyclone;
 +
# Try to synthesize the counter at 250MHz in any other FPGA.
 +
{{collapse bottom}}
 +
 
 +
{{collapse top| Homework 06: Finite State Mahines with Datapath (Deadline: 12/05/2015)}}
 +
In this homework you must produce a report in the format of an article. The article template can be downloaded [https://www.dropbox.com/s/qszkjbid16m414w/lab_report-template.zip?dl=0 here].
 +
The report will describe a lab experiment including the exercises from the Pong Chu book, enumerated bellow.
 +
You must simulate your designs to show that they work properly, and report differences in area and maximum clock among different designs.
 +
Don't forget to include the FSM/FSMD and/or ASM/ASMD in the report.
 +
When modifying a design shown in the book, compare the results with the original design.
 +
 
 +
Exercises:
 +
* Group 1 (names here): 10.3, 10.4, 11.6
 +
* Group 2 (names here): 10.8, 11.7
 +
* Group 3 (names here): 10.10, 11.5
 +
 
 +
{{collapse bottom}}
  
 
= Class log =
 
= Class log =
Linha 109: Linha 175:
 
* Lecture notes 2.
 
* Lecture notes 2.
  
−
 
−
=== Homework 1 ===
 
−
 
−
{{collapse top| Combinational Circuits (Prazo de entrega 19/02/2015)}}
 
−
Download the [[Media:dlp29007-Unidade2_Ex1-2-4.qar | Operator Sharing Source Code (qar)]] or [[Media:dlp29007-lecture02-efficient_comb_circuits-operator_sharing-src.zip | Operator Sharing Source Code (qar.zip)]] and, for each architecture of each one of the three examples, do the following:
 
−
* Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
 
−
* Select the "Fastest" "Speed grade";
 
−
* Select the smallest device available in the family;
 
−
* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
 
−
* Change to the largest device available in the family;
 
−
* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
 
−
 
−
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
 
−
#Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
 
−
#Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?
 
−
 
−
Email the results to the professors until 17/02/2015.
 
−
{{collapse bottom}}
 
  
 
== 19/02: Design of efficient combinational circuits: Function sharing ==
 
== 19/02: Design of efficient combinational circuits: Function sharing ==
Linha 134: Linha 182:
 
* Lecture notes 2.
 
* Lecture notes 2.
  
−
 
−
=== Homework 2 ===
 
−
 
−
{{collapse top| Combinational Circuits (Prazo de entrega 26/02/2015)}}
 
−
Download the [[Media:dlp29007-lecture02-efficient_comb_circuits-function_sharing-src.zip | Function Sharing Source Code (qar.zip)]] and, for each architecture of each one of the examples, do the following:
 
−
* Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
 
−
* Select the "Fastest" "Speed grade";
 
−
* Select the smallest device available in the family;
 
−
* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
 
−
* Change to the largest device available in the family;
 
−
* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
 
−
 
−
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
 
−
#Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
 
−
#Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?
 
−
 
−
Email the results to the professors until next class.
 
−
{{collapse bottom}}
 
  
 
== 26/02: Design of efficient combinational circuits: Layout Considerations ==
 
== 26/02: Design of efficient combinational circuits: Layout Considerations ==
Linha 159: Linha 189:
 
* Lecture notes 2.
 
* Lecture notes 2.
  
−
 
−
=== Homework 3 ===
 
−
 
−
{{collapse top| Combinational Circuits (Prazo de entrega 03/03/2015)}}
 
−
Groups of two students will study and explain to the class one of these circuits in Chapter 7 of bibliographic reference 1: 7.5.2 (Programmable Priority Encoder), 7.5.4 (Combinational Adder-Based Multiplier), 7.5.5 (Hamming Distance Circuit).
 
−
{{collapse bottom}}
 
  
 
== 03/03: Design of efficient combinational circuits: General Circuits ==
 
== 03/03: Design of efficient combinational circuits: General Circuits ==
Linha 188: Linha 212:
 
* Lecture notes 4.
 
* Lecture notes 4.
 
* [http://quartushelp.altera.com/14.0/mergedProjects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_create_clock.htm Quartus II help - create_clock] - ALTERA
 
* [http://quartushelp.altera.com/14.0/mergedProjects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_create_clock.htm Quartus II help - create_clock] - ALTERA
−
 
−
===Homework 4===
 
−
{{collapse top| Projeto sincrono - Timer (HORA, MINUTO, SEGUNDO) - (Prazo de entrega 24/03/2015)}}
 
−
* '''Grupos de 2 alunos!'''
 
−
* Implementar um timer que tenha saída de segundo, minuto e hora (todos em binário).
 
−
:* Versão 1: Utilizando clocks derivados de 1seg, 1min, 1hora, todos a partir de 50 MHz.
 
−
:* Versão 2: Projeto Síncrono com clock global.
 
−
* Simular o timer (versão 1 e 2), mostrando o correto funcionamento.
 
−
* Análisar o RTL e número de elementos necessários.
 
−
* Criar um arquivo '''timer.sdc''' e incluí-lo no projeto (para definir a restrição de tempo do clock máximo)
 
−
create_clock -name CLK50MHz -period 20 [get_ports {clk}]
 
−
ou
 
−
create_clock -name CLK50MHz -period 250MHz [get_ports {clk}]
 
−
*Verificar no '''{Compilation Report > TimeQuest Timing Analyser}''', se o clock máximo do circuito obtido é maior que 50 MHz.
 
−
{{collapse bottom}}
 
−
 
−
===Homework 5===
 
−
 
−
{{collapse top| Sequential Circuits (Prazo de entrega 26/03/2015)}}
 
−
Each student will synthesize and analyze a counter, according to the list bellow. 
 
−
*Danilo: Binary Counter
 
−
*Elton: Decimal Counter
 
−
*Ernani: Gray Counter
 
−
*Jean: Johnson Counter
 
−
*Leonan: LFSR Counter
 
−
*Thiago Henrique: PWM Counter
 
−
*Thiago Werner: Ring Counter
 
−
 
−
Students must:
 
−
# Use synchronous design methodology, with separate segment for memory, next-state logic and output logic;
 
−
# Use a GENERIC constant to define the counter size, and test the counter for 3 and 8 bits.
 
−
# Simular o contador (e variações), mostrando o correto funcionamento.
 
−
# Análisar o RTL e número de elementos necessários, verificar que o clock é global e sem interrupções por portas.
 
−
# Criar um arquivo '''counter.sdc''' e incluí-lo no projeto (para definir a restrição de tempo do clock máximo)
 
−
create_clock -name CLK250MHz -period 250MHz [get_ports {clk}]
 
−
# Report area of the design (and variations);
 
−
# Report maximum delays and clock of the design using the SDC file to set up a target clock;
 
−
# Modify circuits to increase maximum frequency in a Cyclone;
 
−
# Try to synthesize the counter at 250MHz in any other FPGA.
 
−
{{collapse bottom}}
 
−
 
  
  

Edição das 16h36min de 29 de abril de 2015

EngTel: Programmable Logic Devices II - 2015-1

  • Lecturers: Arliones Hoeller e Marcos Moecke
  • Class: 29007
  • Meetings: tuesdays at 9:40 and thursdays at 7:30 at Laboratório de Programação.
  • Extra-class hours:
    • Arliones
      • Tuesdays, 14:30 to 15:30
      • Thursdays, 10:30 to 11:30
    • Marcos
      • Tuesdays, 13:30 to 14:30
      • Thursdays, 10:30 to 11:30

Course Plan (in Portuguese)

Class Schedule

Grades

Registration T0 T1 T2 T3 T4 T5 Final

Class Material

Bibliographic References

  1. Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN 0471720925.
  2. David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, Burlington, 2007, Pages 3-48, ISBN 9780123704979, http://dx.doi.org/10.1016/B978-012370497-9/50002-0.

Lecture Notes

These lecture notes are based on the ones made available by Prof. Pong P. Chu at [1].


Recursos de Laboratório

Para uso fora do IFSC dos recursos computacionais com licença educacional, o IFSC disponibiliza para seus alunos o IFSC-CLOUD. Atualmente a forma mais eficiente de acesso é através do Cliente X2GO. O procedimento de instalação/ configuração e uso do Quartus/Modelsim/QSIM está descrito em Acesso ao IFSC-CLOUD#Cliente X2GO (recomendado).

Para a geração de documentação/relatórios técnicos/artigos, está disponibilizada a plataforma Sharelatex do IFSC-CLOUD. Utilize preferencialmente o modelo de artigo no padrão ABNT.

Homework

Homework 01: Combinational Circuits (Deadline: 19/02/2015)

Download the Operator Sharing Source Code (qar) or Operator Sharing Source Code (qar.zip) and, for each architecture of each one of the three examples, do the following:

  • Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
  • Select the "Fastest" "Speed grade";
  • Select the smallest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
  • Change to the largest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;

Write a report containing the numeric results of your experiments. For each example, answer the following questions:

  1. Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
  2. Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?

Email the results to the professors until 17/02/2015.

Homework 02: Combinational Circuits (Deadline 26/02/2015)

Download the Function Sharing Source Code (qar.zip) and, for each architecture of each one of the examples, do the following:

  • Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
  • Select the "Fastest" "Speed grade";
  • Select the smallest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
  • Change to the largest device available in the family;
  • For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;

Write a report containing the numeric results of your experiments. For each example, answer the following questions:

  1. Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
  2. Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?

Email the results to the professors until next class.

Homework 03: Combinational Circuits (Deadline: 03/03/2015)

Groups of two students will study and explain to the class one of these circuits in Chapter 7 of bibliographic reference 1: 7.5.2 (Programmable Priority Encoder), 7.5.4 (Combinational Adder-Based Multiplier), 7.5.5 (Hamming Distance Circuit).

Homework 04: Synchronous Project - Timer (hour, minute, second) - (Deadline: 24/03/2015)
  • Groups of 2 students!
  • Implement a timer with outputs seconds, minutes and hour (in binary mode);
  • Version 1: Use derived clocks of 1 second, 1 minute, and 1 hour, all from a 50 MHz source.
  • Version 2: Build a synchronous desing using a global clock.
  • Simulate the timer (both versions), showing the correct behaviour.
  • Analyse the RTL and report the number of logic elements used.
  • Create a timer.sdc file and include it in the project (to define a clock restriction)
create_clock -name CLK50MHz -period 20 [get_ports {clk}]

OR 

create_clock -name CLK50MHz -period 250MHz [get_ports {clk}]
  • Check at {Compilation Report > TimeQuest Timing Analyser} if the maximum clock of the circuit is greater than 50 MHz.
Homework 05: Sequential Circuits (Deadline: 26/03/2015)

Each student will synthesize and analyze a counter, according to the list bellow.

  • Danilo: Binary Counter
  • Elton: Decimal Counter
  • Ernani: Gray Counter
  • Jean: Johnson Counter
  • Leonan: LFSR Counter
  • Thiago Henrique: PWM Counter
  • Thiago Werner: Ring Counter

Students must:

  1. Use synchronous design methodology, with separate segment for memory, next-state logic and output logic;
  2. Use a GENERIC constant to define the counter size, and test the counter for 3 and 8 bits.
  3. Simulate the counter (and variations), showing the correct behaviour.
  4. Analyze the RTL and report the number of logic elements used. Observe that the clock is global and without interruptions by ports.
  5. Create a counter.sdc file and include it in the project (to define a clock restriction)
create_clock -name CLK250MHz -period 250MHz [get_ports {clk}]
  1. Report area of the design (and variations);
  2. Report maximum delays and clock of the design using the SDC file to set up a target clock;
  3. Modify circuits to increase maximum frequency in a Cyclone;
  4. Try to synthesize the counter at 250MHz in any other FPGA.
Homework 06: Finite State Mahines with Datapath (Deadline: 12/05/2015)

In this homework you must produce a report in the format of an article. The article template can be downloaded here. The report will describe a lab experiment including the exercises from the Pong Chu book, enumerated bellow. You must simulate your designs to show that they work properly, and report differences in area and maximum clock among different designs. Don't forget to include the FSM/FSMD and/or ASM/ASMD in the report. When modifying a design shown in the book, compare the results with the original design.

Exercises:

  • Group 1 (names here): 10.3, 10.4, 11.6
  • Group 2 (names here): 10.8, 11.7
  • Group 3 (names here): 10.10, 11.5

Class log

05/02: Course presentation. Complexity Management. Overview of Complex Digital Systems Desgin.

Recommended reading

  • Chapter 1 of bibliographic references 1 AND 2.
  • Lecture notes 1.


12/02 - 26/02: Design of efficient combinational circuits

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.
  • TimeQuest Help, mainly Propagation Delay Report.

12/02: Design of efficient combinational circuits: Operator sharing

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


19/02: Design of efficient combinational circuits: Function sharing

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


26/02: Design of efficient combinational circuits: Layout Considerations

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.


03/03: Design of efficient combinational circuits: General Circuits

Students presented and discussed the general circuits of section 7.5 of bibliographic reference 1.

Recommended reading

  • Chapter 7 of bibliographic reference 1.
  • Lecture notes 2.

06/03: Design of efficient sequential circuits: principle

Recommended reading

  • Chapter 8 of bibliographic reference 1.
  • Lecture note 3.

12/03, 17/03, 26/03 and 31/03: Design of efficient sequential circuits: principle and practice

Recommended reading

  • Chapter 8 of bibliographic reference 1.
  • Chapter 9 of bibliographic reference 1.
  • Lecture notes 3.
  • Lecture notes 4.
  • Quartus II help - create_clock - ALTERA


07/04, 10/04 and 17/04: Design of Efficient Finite State Machines: principle and practice

Recommended reading

  • Chapter 10 of bibliographic reference 1.
  • Lecture notes 5.


23/04: Register Transfer Methodology: Principle

Recommended reading

  • Chapter 11 of bibliographic reference 1.
  • Lecture notes 6.
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