Circuito Somador e Subtrator - Pedroni

Código VHDL

--Book: Pedroni/491
--8 bits
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity add_sub is
	
	generic (
		n: natural := 8);
	
	port(
		a,b: in std_logic_vector (n-1 downto 0);
		sum, sub: out std_logic_vector (n-1 downto 0));
end entity;

architecture add_sub of add_sub is
	signal sum_sig, sub_sig : signed (n-1 downto 0);

	begin
		--Convert to signed and add_sub
		sum_sig <= signed(a) + signed(b);
		sub_sig <= signed(a) - signed(b);
		--Return to std_logic_vector
		sum <= std_logic_vector (sum_sig);
		sub <= std_logic_vector (sub_sig);

end architecture;

Testbench

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Simulações

Nº Bits	ALMs	Delay	Potência (mW)
x	x	x	x
x	x	x	x
x	x	x	x
x	x	x	x