Circuito Somador e Subtrator - Pedroni
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Estrutura
- Realiza a soma simples através do operador '+'.
VHDL
| Código |
|---|
--Book: Pedroni/491
--8 bits
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_sub is
generic (n: natural := 4);
port(
a,b: in std_logic_vector (n-1 downto 0);
--sub : out std_logic_vector (n-1 downto 0));
sum : out std_logic_vector (n-1 downto 0));
end entity;
architecture add_sub of add_sub is
signal sum_sig : signed (n-1 downto 0);
--signal sub_sig : signed (n-1 downto 0);
begin
--Convert to signed and add_sub
sum_sig <= signed(a) + signed(b);
--sub_sig <= signed(a) - signed(b);
--Return to std_logic_vector
sum <= std_logic_vector (sum_sig);
--sub <= std_logic_vector (sub_sig);
end architecture;
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- Logic Block:
Simulações
| Nº Bits | ALMs | Potência (mW) | Report Path | Report Timing | Caminho crítico | Logic Block | Optimization | Seed |
|---|---|---|---|---|---|---|---|---|
| 4 | 34 | 142.03 | 3.035 | 3.267 | dout[0]-internal[3] | S | Balanced | 1 |
| 32 | 234 | 185.14 | 5.481 | 5.713 | dout[0]-internal[31] | S | Balanced | 1 |
| 128 | 882 | 306.90 | 13.062 | 13.294 | deserial1-dout[0]-internal[127] | Auto | Balanced | 1 |