Carry Lookahead 8 bits
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--Book: Eletronica digital moderna e VHDL/490 - Pelo autor
-- Carry lookahead com 8 bits
--
architecture adder_carry_lookahead_8 of adder is
signal carry: std_logic_vector(n/8 downto 0);
component carry_lookahead_adder_8 is
port( a,b : in std_logic_vector(7 downto 0);
cin: in std_logic;
cout: out std_logic;
sum: out std_logic_vector(7 downto 0));
end component;
begin
carry(0) <= cin;
gen_adder: for i in 1 to n/8 generate
adder: carry_lookahead_adder_8
port map(
a => a(8*i-1 downto 8*i-8),
b => b(8*i-1 downto 8*i-8),
cin => carry(i-1),
sum => sum(8*i-1 downto 8*i-8),
cout => carry(i)
);
end generate;
end architecture;