Carry Lookahead 8 bits

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--Book: Eletronica digital moderna e VHDL/490 - Pelo autor
-- Carry lookahead com 8 bits
--

architecture adder_carry_lookahead_8 of adder is

	signal carry: std_logic_vector(n/8  downto 0); 
	
	component carry_lookahead_adder_8 is
			port( a,b : in std_logic_vector(7 downto 0);
			cin: in std_logic;
			cout: out std_logic;
			sum: out std_logic_vector(7 downto 0));
	end component;
	
begin
	carry(0) <= cin;
	gen_adder: for i in 1 to n/8 generate
		adder: carry_lookahead_adder_8 
			port map(
				a => a(8*i-1 downto 8*i-8),
				b => b(8*i-1 downto 8*i-8),
				cin => carry(i-1),
				sum => sum(8*i-1 downto 8*i-8),
				cout => carry(i)
			);
		end generate;
		
end architecture;

---------------------------------------------------
--Book: Pedroni/490
--8 bits carry-lookahead
--Uso do component
library ieee;
use ieee.std_logic_1164.all;

entity carry_lookahead_adder_8  is
	port( a,b : in std_logic_vector(7 downto 0);
			cin: in std_logic;
			cout: out std_logic;
			sum: out std_logic_vector(7 downto 0));
end entity;

architecture structure of carry_lookahead_adder_8 is
		signal g,p,c : std_logic_vector(7 downto 0);
	
	begin	
	---computation of g and p;
		g <= a and b; 
		p <= a xor b;
		
	---computation of carry;
		c(0) <= cin;
		c(1) <= g(0) or 
				 (p(0) and cin);
				 
		c(2) <= g(1) or
				 (p(1) and g(0)) or 	 
				 (p(1) and p(0) and cin);

		c(3) <= g(2) or
				 (p(2) and g(1)) or
				 (p(2) and p(1) and g(0)) or
				 (p(2) and p(1) and p(0) and cin);
				  
		c(4) <= g(3) or 
				 (p(3) and g(2)) or
				 (p(3) and p(2) and g(1)) or		 
				 (p(3) and p(2) and p(1) and g(0)) or
				 (p(3) and p(2) and p(1) and p(0) and cin); 
				 
		c(5) <= g(4) or 
				 (p(4) and g(3)) or
				 (p(4) and p(3) and g(2)) or
				 (p(4) and p(3) and p(2) and g(1)) or
				 (p(4) and p(3) and p(2) and p(1) and g(0)) or 
				 (p(4) and p(3) and p(2) and p(1) and p(0) and cin);		 				 

			
		c(6) <= g(5) or
				 (p(5) and g(4)) or 
				 (p(5) and p(4) and g(3)) or
				 (p(5) and p(4) and p(3) and g(2)) or
				 (p(5) and p(4) and p(3) and p(2) and g(1)) or
				 (p(5) and p(4) and p(3) and p(2) and p(1) and g(0)) or 
				 (p(5) and p(4) and p(3) and p(2) and p(1) and p(0) and cin); 		
		
		c(7) <= g(6) or
				 (p(6) and g(5)) or
				 (p(6) and p(5) and g(4)) or
				 (p(6) and p(5) and p(4) and g(3)) or
				 (p(6) and p(5) and p(4) and p(3) and g(2)) or
				 (p(6) and p(5) and p(4) and p(3) and p(2) and g(1)) or
				 (p(6) and p(5) and p(4) and p(3) and p(2) and p(1) and g(0)) or
				 (p(6) and p(5) and p(4) and p(3) and p(2) and p(1) and p(0) and cin); 
		
		cout <= g(7) or
				 (p(7) and g(6)) or
				 (p(7) and p(6) and g(5)) or
				 (p(7) and p(6) and p(5) and g(4)) or
				 (p(7) and p(6) and p(5) and p(4) and g(3)) or
				 (p(7) and p(6) and p(5) and p(4) and p(3) and g(2)) or	
				 (p(7) and p(6) and p(5) and p(4) and p(3) and p(2) and g(1)) or
				 (p(7) and p(6) and p(5) and p(4) and p(3) and p(2) and p(1) and g(0)) or 
				 (p(7) and p(6) and p(5) and p(4) and p(3) and p(2) and p(1) and p(0) and cin); 					 
				 
	---computation of sum
	sum <= p xor c;
	
end architecture;