Circuito Somador e Subtrator - Pedroni
Ir para navegação
Ir para pesquisar
Estrutura
- Realiza a soma simples através do operador '+'.
VHDL
Código |
---|
--Book: Pedroni/491
--8 bits
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_sub is
generic (n: natural := 4);
port(
a,b: in std_logic_vector (n-1 downto 0);
--sub : out std_logic_vector (n-1 downto 0));
sum : out std_logic_vector (n-1 downto 0));
end entity;
architecture add_sub of add_sub is
signal sum_sig : signed (n-1 downto 0);
--signal sub_sig : signed (n-1 downto 0);
begin
--Convert to signed and add_sub
sum_sig <= signed(a) + signed(b);
--sub_sig <= signed(a) - signed(b);
--Return to std_logic_vector
sum <= std_logic_vector (sum_sig);
--sub <= std_logic_vector (sub_sig);
end architecture;
|
- Chip planner:
Simulações
Nº Bits | ALMs | Potência (mW) | Report Path | Report Timing |
---|---|---|---|---|
4 | x | x | x | x |
32 | x | x | x | x |
128 | x | x | x | x |