Mudanças entre as edições de "DLP29007-2015-1"
Linha 174: | Linha 174: | ||
* Lecture note 3. | * Lecture note 3. | ||
− | == 12/03 and | + | == 12/03, 17/03, 26/03 and 30/03: Design of efficient sequential circuits: principle and practice == |
=== Recommended reading === | === Recommended reading === |
Edição das 23h46min de 30 de março de 2015
EngTel: Programmable Logic Devices II - 2015-1
- Lecturers: Arliones Hoeller e Marcos Moecke
- Class: 29007
- Meetings: tuesdays at 9:40 and thursdays at 7:30 at Laboratório de Programação.
- Extra-class hours:
- Arliones: tuesdays from 13:30 until 15:20
- Marcos:
Course Plan (in Portuguese)
Class Schedule
Grades
Registration | T0 | T1 | T2 | T3 | T4 | T5 | Final |
---|---|---|---|---|---|---|---|
Class Material
Bibliographic References
- Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN 0471720925.
- David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, Burlington, 2007, Pages 3-48, ISBN 9780123704979, http://dx.doi.org/10.1016/B978-012370497-9/50002-0.
Lecture Notes
These lecture notes are based on the ones made available by Prof. Pong P. Chu at [1].
- Lecture 01: Complexity Mangement and the Design of Complex Digital Systems
- Lecture 02: Efficient Design of Combinational Circuits
- Lecture 03: Efficient Design of Sequential Circuits
- Lecture 04: Design of Sequential Circuits: Practice
Recursos de Laboratório
Para uso fora do IFSC dos recursos computacionais com licença educacional, o IFSC disponibiliza para seus alunos o IFSC-CLOUD. Atualmente a forma mais eficiente de acesso é através do Cliente X2GO. O procedimento de instalação/ configuração e uso do Quartus/Modelsim/QSIM está descrito em Acesso ao IFSC-CLOUD#Cliente X2GO (recomendado).
Para a geração de documentação/relatórios técnicos/artigos, está disponibilizada a plataforma Sharelatex do IFSC-CLOUD. Utilize preferencialmente o modelo de artigo no padrão ABNT.
Homework
Homework | Deadline |
---|---|
Homework 1: Operator Sharing | 19/02 |
Homework 2: Function Sharing | 26/02 |
Homework 3: Combinational Circuits | 03/03 |
Homework 4: Derived Clocks | 24/03 |
Homework 5: Sequential Circuits | 26/03 |
Class log
05/02: Course presentation. Complexity Management. Overview of Complex Digital Systems Desgin.
Recommended reading
- Chapter 1 of bibliographic references 1 AND 2.
- Lecture notes 1.
12/02 - 26/02: Design of efficient combinational circuits
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
- TimeQuest Help, mainly Propagation Delay Report.
12/02: Design of efficient combinational circuits: Operator sharing
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
Homework 1
Combinational Circuits (Prazo de entrega 19/02/2015) |
---|
Download the Operator Sharing Source Code (qar) or Operator Sharing Source Code (qar.zip) and, for each architecture of each one of the three examples, do the following:
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
Email the results to the professors until 17/02/2015. |
19/02: Design of efficient combinational circuits: Function sharing
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
Homework 2
Combinational Circuits (Prazo de entrega 26/02/2015) |
---|
Download the Function Sharing Source Code (qar.zip) and, for each architecture of each one of the examples, do the following:
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
Email the results to the professors until next class. |
26/02: Design of efficient combinational circuits: Layout Considerations
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
Homework 3
Combinational Circuits (Prazo de entrega 03/03/2015) |
---|
Groups of two students will study and explain to the class one of these circuits in Chapter 7 of bibliographic reference 1: 7.5.2 (Programmable Priority Encoder), 7.5.4 (Combinational Adder-Based Multiplier), 7.5.5 (Hamming Distance Circuit). |
03/03: Design of efficient combinational circuits: General Circuits
Students presented and discussed the general circuits of section 7.5 of bibliographic reference 1.
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
06/03: Design of efficient sequential circuits: principle
Recommended reading
- Chapter 8 of bibliographic reference 1.
- Lecture note 3.
12/03, 17/03, 26/03 and 30/03: Design of efficient sequential circuits: principle and practice
Recommended reading
- Chapter 8 of bibliographic reference 1.
- Chapter 9 of bibliographic reference 1.
- Lecture notes 3.
- Lecture notes 4.
- Quartus II help - create_clock - ALTERA
Homework 4
Projeto sincrono - Timer (HORA, MINUTO, SEGUNDO) - (Prazo de entrega 24/03/2015) |
---|
create_clock -name CLK50MHz -period 20 [get_ports {clk}] ou create_clock -name CLK50MHz -period 250MHz [get_ports {clk}]
|
Homework 5
Sequential Circuits (Prazo de entrega 26/03/2015) |
---|
Each student will synthesize and analyze a counter, according to the list bellow.
Students must:
create_clock -name CLK250MHz -period 250MHz [get_ports {clk}]
|