DLP29007-2015-1

EngTel: Programmable Logic Devices II - 2015-1

• Lecturers: Arliones Hoeller e Marcos Moecke
• Class: 29007
• Meetings: tuesdays at 9:40 and thursdays at 7:30 at Laboratório de Programação.
• Extra-class hours:
  • Arliones: tuesdays from 13:30 until 15:20
  • Marcos:

Grades

Registration	T0	T1	T2	T3	T4	T5	Final

Class Material

Bibliographic References

1. Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN 0471720925.
2. David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, Burlington, 2007, Pages 3-48, ISBN 9780123704979, http://dx.doi.org/10.1016/B978-012370497-9/50002-0.

Lecture Notes

• Lecture 01: Complexity Mangement and the Design of Complex Digital Systems
• Lecture 02: Efficient Design of Combinational Circuits

Laboratory resources

• 2-1: Operator Sharing Source Code

Homework

• Homework 1: Operator Sharing

Class log

05/02: Course presentation. Complexity Management. Overview of Complex Digital Systems Desgin.

Recommended reading

• Chapter 1 of bibliographic references 1 AND 2.
• Lecture notes 1.

12/02 - 26/02: Design of efficient combinational circuits

Recommended reading

• Chapter 7 of bibliographic reference 1.
• Lecture notes 2.

12/02: Design of efficient combinational circuits: Operator sharing

Recommended reading

• Chapter 7 of bibliographic reference 1.
• Lecture notes 2.

Homework 1

Download the 2-1: Operator Sharing Source Code and, for each architecture of each one of the three examples, do the following:

• Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
• Select the "Fastest" "Speed grade";
• Select the smallest device available in the family;
• Compile the example, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
• Change to the largest device available in the family;
• Compile the example, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;

Write a report containing the numeric results of your experiments. For each example, answer the following questions:

1. Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
2. Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?

Email the results to the professors until 17/02/2015.