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Email the results to the professors until 17/02/2015. | Email the results to the professors until 17/02/2015. | ||
+ | |||
+ | |||
+ | == 19/02: Design of efficient combinational circuits: Function sharing == | ||
+ | |||
+ | === Recommended reading === | ||
+ | * Chapter 7 of bibliographic reference 1. | ||
+ | * Lecture notes 2. | ||
+ | |||
+ | |||
+ | === Homework 2 === | ||
+ | |||
+ | Download the [[Media:dlp29007-Unidade2_funcshar.qar | Function Sharing Source Code (qar)]] or [[Media:dlp29007-lecture02-efficient_comb_circuits-function_sharing-src.zip | Function Sharing Source Code (qar.zip)]] and, for each architecture of each one of the examples, do the following: | ||
+ | * Choose one of the available FPGA families for your project (e.g. Cyclone IV GX); | ||
+ | * Select the "Fastest" "Speed grade"; | ||
+ | * Select the smallest device available in the family; | ||
+ | * For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit; | ||
+ | * Change to the largest device available in the family; | ||
+ | * For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit; | ||
+ | |||
+ | Write a report containing the numeric results of your experiments. For each example, answer the following questions: | ||
+ | #Was there any differences between the RTL generated for each architecture? Why did this happen (or not)? | ||
+ | #Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)? | ||
+ | |||
+ | Email the results to the professors until next class. |
Edição das 16h42min de 25 de fevereiro de 2015
EngTel: Programmable Logic Devices II - 2015-1
- Lecturers: Arliones Hoeller e Marcos Moecke
- Class: 29007
- Meetings: tuesdays at 9:40 and thursdays at 7:30 at Laboratório de Programação.
- Extra-class hours:
- Arliones: tuesdays from 13:30 until 15:20
- Marcos:
Course Plan (in Portuguese)
Class Schedule
Grades
Registration | T0 | T1 | T2 | T3 | T4 | T5 | Final |
---|---|---|---|---|---|---|---|
Class Material
Bibliographic References
- Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN 0471720925.
- David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, Burlington, 2007, Pages 3-48, ISBN 9780123704979, http://dx.doi.org/10.1016/B978-012370497-9/50002-0.
Lecture Notes
- Lecture 01: Complexity Mangement and the Design of Complex Digital Systems
- Lecture 02: Efficient Design of Combinational Circuits
Laboratory resources
Homework
Class log
05/02: Course presentation. Complexity Management. Overview of Complex Digital Systems Desgin.
Recommended reading
- Chapter 1 of bibliographic references 1 AND 2.
- Lecture notes 1.
12/02 - 26/02: Design of efficient combinational circuits
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
- TimeQuest Help, mainly Propagation Delay Report.
12/02: Design of efficient combinational circuits: Operator sharing
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
Homework 1
Download the Operator Sharing Source Code (qar) or Operator Sharing Source Code (qar.zip) and, for each architecture of each one of the three examples, do the following:
- Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
- Select the "Fastest" "Speed grade";
- Select the smallest device available in the family;
- For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
- Change to the largest device available in the family;
- For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
- Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
- Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?
Email the results to the professors until 17/02/2015.
19/02: Design of efficient combinational circuits: Function sharing
Recommended reading
- Chapter 7 of bibliographic reference 1.
- Lecture notes 2.
Homework 2
Download the Function Sharing Source Code (qar) or Function Sharing Source Code (qar.zip) and, for each architecture of each one of the examples, do the following:
- Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
- Select the "Fastest" "Speed grade";
- Select the smallest device available in the family;
- For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
- Change to the largest device available in the family;
- For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
Write a report containing the numeric results of your experiments. For each example, answer the following questions:
- Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
- Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?
Email the results to the professors until next class.