Edição das 11h50min de 6 de outubro de 2015

EngTel: Dispositivos Lógicos Programáveis II

Professores: Arliones Hoeller e Marcos Moecke
Turma: 29007
Encontros: semanalmente nas terças e quinzenalmente nas quartas às 15:40 no Laboratório de Programação.
Atendimento Extra-classe:
- Arliones
  - Terças das 9:40 às 10:35
  - Quintas das 13:30 às 14:25
- Marcos

Material das Aulas

Referências Bibliográficas

Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. Wiley-IEEE Press, Hoboken, 2006, Pages 1-22, ISBN 0471720925.
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Morgan Kaufmann, Burlington, 2007, Pages 3-48, ISBN 9780123704979, http://dx.doi.org/10.1016/B978-012370497-9/50002-0.

Notas de aulas

Estas notas de aula são baseadas nas dispobilizadas pelo Prof. Pong P. Chu em [1].

Recursos de Laboratório

Para uso fora do IFSC dos recursos computacionais com licença educacional, o IFSC disponibiliza para seus alunos o IFSC-CLOUD. Atualmente a forma mais eficiente de acesso é através do Cliente X2GO. O procedimento de instalação/ configuração e uso do Quartus/Modelsim/QSIM está descrito em Acesso ao IFSC-CLOUD#Cliente X2GO (recomendado).

Para a geração de documentação/relatórios técnicos/artigos, está disponibilizada a plataforma Sharelatex do IFSC-CLOUD. Utilize preferencialmente o modelo de artigo no padrão ABNT.

Diário de Aulas

28/07: Laboratório: Processadores Embarcados (SoC)

Nesta aula nós seguiremos um tutorial da Altera para construir um System-on-a-Chip (SoC), sintetizando um processador softcore NIOS em uma FPGA e carregando um software nele. Nas próximas aulas nós integraremos nossa própria lógica neste processador. Esta arquitetura de sistema deverá ser empregada em todos os trabalhos ao longo do semestre.

A figura abaixo dá uma visão geral do que iremos implementar:

Você precisará destes documentos para desenvolver este tutorial:

Recomenda-se seguir este roteiro:

Analisar e debater figura 1-1 na página 1-2;
Destacar os requisitos de hardware para o experimento na página 1-3;
Analisar e debater o fluxo de desenvolvimento de projeto da figura 1-2 na página 1-4;
Debater as questões de análise de requisitos do sistema na página 1-5;
Partir para criação do exemplo na página 1-8;
Seguir tutorial (passos importantes destacados no PDF);

Se o Eclipse SBT do Nios II não inicializar em um sistema Ubuntu 14.04 ou mais recente, você precisa instalar a libGTK2:

sudo apt-get install libgtk2.0-0:i386

@@ Linha 1: / Linha 1: @@
-Originalmente publicada em [[DLP29007-2015-2]].
+= EngTel: Dispositivos Lógicos Programáveis II =
-= EngTel: Dispositivos Lógicos Programáveis II - 2015-2 =
 *'''Professores:''' [[Arliones Hoeller]] e [[Marcos Moecke]]
@@ Linha 12: / Linha 10: @@
 **Marcos
 ***
+***
 == [[DLP2-EngTel_(Plano_de_Ensino)|'''Plano de Ensino''']] ==
@@ Linha 28: / Linha 27: @@
 Estas notas de aula são baseadas nas dispobilizadas pelo Prof. Pong P. Chu em [http://academic.csuohio.edu/chu_p/rtl/rtl_hardware.html].
-* [[Media:dlp29007-lecture01-complexity.pdf | Lecture 01: Complexity Mangement and the Design of Complex Digital Systems]]
+* [http://docente.ifsc.edu.br/arliones.hoeller/dlp2/slides/dlp29007-lecture01-complexity.pdf Lecture 01: Complexity Mangement and the Design of Complex Digital Systems]
-* [[Media:dlp29007-lecture02-efficient_comb_circuits.pdf | Lecture 02: Efficient Design of Combinational Circuits]]
+* [http://docente.ifsc.edu.br/arliones.hoeller/dlp2/slides/dlp29007-lecture02-efficient_comb_circuits.pdf Lecture 02: Efficient Design of Combinational Circuits]
-* [https://www.dropbox.com/s/j8pbw4nm8vg9ybd/dlp29007-lecture03-efficient_seq_circuits.pdf?dl=0 Lecture 03: Efficient Design of Sequential Circuits]
+* [http://docente.ifsc.edu.br/arliones.hoeller/dlp2/slides/dlp29007-lecture03-efficient_seq_circuits.pdf Lecture 03: Efficient Design of Sequential Circuits]
-* [https://www.dropbox.com/s/6safyxmvm0444zf/dlp29007-lecture04-sequetial_circuit_design.pdf?dl=0 Lecture 04: Design of Sequential Circuits: Practice]
+* [http://docente.ifsc.edu.br/arliones.hoeller/dlp2/slides/dlp29007-lecture04-sequetial_circuit_design.pdf Lecture 04: Design of Sequential Circuits: Practice]
-* [https://www.dropbox.com/s/ol888ifacn5gx1e/dlp29007-lecture05-fsm.pdf?dl=0 Lecture 05: Finite State Machines: Principle and Practice]
+* [http://docente.ifsc.edu.br/arliones.hoeller/dlp2/slides/dlp29007-lecture05-fsm.pdf Lecture 05: Finite State Machines: Principle and Practice]
-* [https://www.dropbox.com/s/zqrvwyzbbcdf1m2/dlp29007-lecture06-register_transfer.pdf?dl=0 Lecture 06: Register Transfer Methodology: Principle]
+* [http://docente.ifsc.edu.br/arliones.hoeller/dlp2/slides/dlp29007-lecture06-register_transfer.pdf Lecture 06: Register Transfer Methodology: Principle]
-* [https://www.dropbox.com/s/zqrvwyzbbcdf1m2/dlp29007-lecture07-register_transfer.pdf?dl=0 Lecture 07: Register Transfer Methodology: Practice]
-* [https://www.dropbox.com/s/5sj2vnsznjvuzn3/chap13.pdf?dl=0 Lecture 08: Hierarchical Design]
-* [ Lecture 09: Parameterized Design: Principle]
-* [ Lecture 10: Parameterized Design: Practice]
-* [ Lecture 11: Clock and Synchronization: Principle and Practice]
-<!--
+* [http://tdb Lecture 07: Register Transfer Methodology: Practice]
-* [[Media:dlp29007-lecture03-efficient_seq_circuits.pdf | Lecture 03: Efficient Design of Sequential Circuits]]
+* [http://tdb Lecture 08: Hierarchical Design]
-Sugestão: Só tornar permanente depois que não tiver mais alterações.
+* [http://tdb Lecture 09: Parameterized Design: Principle]
--->
+* [http://tdb Lecture 10: Parameterized Design: Practice]
+* [http://tdb Lecture 11: Clock and Synchronization: Principle and Practice]
 == Recursos de Laboratório ==
@@ Linha 50: / Linha 44: @@
 Para a geração de documentação/relatórios técnicos/artigos, está disponibilizada a plataforma  [http://200.135.233.26:3000/project Sharelatex do IFSC-CLOUD]. Utilize preferencialmente o [http://200.135.233.26:3000/project/54750cb57ae8187440d60acd  modelo de artigo no padrão ABNT].
-<!--
-== Homework ==
-{{collapse top| Homework 01: Combinational Circuits (Deadline: 19/02/2015)}}
-Download the [[Media:dlp29007-Unidade2_Ex1-2-4.qar | Operator Sharing Source Code (qar)]] or [[Media:dlp29007-lecture02-efficient_comb_circuits-operator_sharing-src.zip | Operator Sharing Source Code (qar.zip)]] and, for each architecture of each one of the three examples, do the following:
-* Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
-* Select the "Fastest" "Speed grade";
-* Select the smallest device available in the family;
-* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
-* Change to the largest device available in the family;
-* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
-Write a report containing the numeric results of your experiments. For each example, answer the following questions:
-#Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
-#Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?
-Email the results to the professors until 17/02/2015.
-{{collapse bottom}}
-{{collapse top| Homework 02: Combinational Circuits (Deadline 26/02/2015)}}
-Download the [[Media:dlp29007-lecture02-efficient_comb_circuits-function_sharing-src.zip | Function Sharing Source Code (qar.zip)]] and, for each architecture of each one of the examples, do the following:
-* Choose one of the available FPGA families for your project (e.g. Cyclone IV GX);
-* Select the "Fastest" "Speed grade";
-* Select the smallest device available in the family;
-* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
-* Change to the largest device available in the family;
-* For each architecture of the example, compile the it, analyze the RTL output, and take note of the number of logic elements/LUTs consumed, and of the highest delay in the circuit;
-Write a report containing the numeric results of your experiments. For each example, answer the following questions:
-#Was there any differences between the RTL generated for each architecture? Why did this happen (or not)?
-#Was there any differences between the RTL generated, for the same architecture, for different devices? Why did this happen (or not)?
-Email the results to the professors until next class.
-{{collapse bottom}}
-{{collapse top| Homework 03: Combinational Circuits (Deadline: 03/03/2015)}}
-Groups of two students will study and explain to the class one of these circuits in Chapter 7 of bibliographic reference 1: 7.5.2 (Programmable Priority Encoder), 7.5.4 (Combinational Adder-Based Multiplier), 7.5.5 (Hamming Distance Circuit).
-{{collapse bottom}}
-{{collapse top| Homework 04: Synchronous Project - Timer (hour, minute, second) - (Deadline: 24/03/2015)}}
-* '''Groups of 2 students!'''
-* Implement a timer with outputs seconds, minutes and hour (in binary mode);
-* Version 1: Use derived clocks of 1 second, 1 minute, and 1 hour, all from a 50 MHz source.
-* Version 2: Build a synchronous desing using a global clock.
-* Simulate the timer (both versions), showing the correct behaviour.
-* Analyse the RTL and report the number of logic elements used.
-* Create a '''timer.sdc''' file and include it in the project (to define a clock restriction)
- create_clock -name CLK50MHz -period 20 [get_ports {clk}]
-OR
- create_clock -name CLK50MHz -period 250MHz [get_ports {clk}]
-* Check at '''{Compilation Report > TimeQuest Timing Analyser}''' if the maximum clock of the circuit is greater than 50 MHz.
-{{collapse bottom}}
-{{collapse top| Homework 05: Sequential Circuits (Deadline: 26/03/2015)}}
-Each student will synthesize and analyze a counter, according to the list bellow.
-*Danilo: Binary Counter
-*Elton: Decimal Counter
-*Ernani: Gray Counter
-*Jean: Johnson Counter
-*Leonan: LFSR Counter
-*Thiago Henrique: PWM Counter
-*Thiago Werner: Ring Counter
-Students must:
-# Use synchronous design methodology, with separate segment for memory, next-state logic and output logic;
-# Use a GENERIC constant to define the counter size, and test the counter for 3 and 8 bits.
-# Simulate the counter (and variations), showing the correct behaviour.
-# Analyze the RTL and report the number of logic elements used. Observe that the clock is global and without interruptions by ports.
-# Create a '''counter.sdc''' file and include it in the project (to define a clock restriction)
- create_clock -name CLK250MHz -period 250MHz [get_ports {clk}]
-# Report area of the design (and variations);
-# Report maximum delays and clock of the design using the SDC file to set up a target clock;
-# Modify circuits to increase maximum frequency in a Cyclone;
-# Try to synthesize the counter at 250MHz in any other FPGA.
-{{collapse bottom}}
-{{collapse top| Homework 06: Finite State Mahines with Datapath (Deadline: 19/05/2015)}}
-In this homework you must produce a report in the format of an article. The article template can be downloaded [https://www.dropbox.com/s/qszkjbid16m414w/lab_report-template.zip?dl=0 here].
-The report will describe a lab experiment including the exercises from the Pong Chu book, enumerated bellow.
-You must simulate your designs to show that they work properly, and report differences in area and maximum clock among different designs.
-Don't forget to include the FSM/FSMD and/or ASM/ASMD in the report.
-When modifying a design shown in the book, compare the results with the original design.
-Exercises:
-* Group 1 (names here): 10.3, 10.4, 11.6
-* Group 2 Elton e Thiago Henrique: 10.8, 11.7
-* Group 3 Leonan e Thiago Werner: 10.10, 11.5
-{{collapse bottom}}
--->
 = Diário de Aulas =
@@ Linha 154: / Linha 57: @@
 Você precisará destes documentos para desenvolver este tutorial:
-* [https://www.dropbox.com/s/woxn6juwq0ikctf/tt_nios2_hardware_tutorial-with_markings.pdf?dl=1 Tutorial com pontos importantes destacados.]
+* [http://docente.ifsc.edu.br/arliones.hoeller/dlp2/docs/tt_nios2_hardware_tutorial-with_markings.pdf Tutorial com pontos importantes destacados.]
 * [https://www.altera.com/content/dam/altera-www/global/en_US/others/literature/tt/niosii_hw_dev_tutorial.zip Código-base para início do tutorial]
 * [http://www.macnicadhw.com.br/c/document_library/get_file?uuid=0612db45-0434-4737-a380-ac846cf662b3&groupId=10157 Esquemático da MercurioIV]

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Edição das 11h50min de 6 de outubro de 2015

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EngTel: Dispositivos Lógicos Programáveis II

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