Circuito Somador Carry Ripple - Pedroni

Código VHDL

--Book: Pedroni/488
--8 bits
library ieee;
use ieee.std_logic_1164.all;

entity carry_ripple_adder is
	generic (n: integer := 8); --number of bits
	
	port (a,b : in std_logic_vector (n-1 downto 0); 
	      cin: in std_logic;
			s: out std_logic_vector (n-1 downto 0);
			cout: out std_logic);
			
end carry_ripple_adder;

architecture structure of carry_ripple_adder is
begin
	process (a,b,cin)
		variable carry: std_logic_vector (n downto 0);
		begin
			for i in 0 to n-1 loop
				s(i) <=  a(i) xor b(i) xor carry(i);
				carry(i+1) := (a(i) and b(i)) or (a(i) and carry(i)) or (b(i) and carry(i));
			end loop;
			cout <= carry(n);
	end process;			
end architecture;

Testbench

• Código
• Resultado (print)

Simulações

Nº Bits	ALMs	Delay	Potência
x	x	x	x
x	x	x	x
x	x	x	x
x	x	x	x