Circuito Somador Carry Lookahead - Pedroni

Código VHDL

--Book: Pedroni/490
--4 bits carry-lookahead
--Uso do component
library ieee;
use ieee.std_logic_1164.all;

entity carry_lookahead_adder is
	port( a,b : in std_logic_vector(3 downto 0);
			cin: in std_logic;
			sum: out std_logic_vector(3 downto 0);
			cout: out std_logic);
			
	end entity;

architecture structure of carry_lookahead_adder is
		signal g,p,c : std_logic_vector(3 downto 0);
	begin	
	---computation of g and p;
		g <= a and b; 
		p <= a xor b;
		
	---computation of carry;
		c(0) <= cin;
		c(1) <= g(0) or (p(0) and cin);
		c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and cin);
		c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and p(0) and cin);
		cout <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1)) or 
							 (p(3) and p(2) and p(1) and g(0)) or 
							 (p(3) and p(2) and p(1) and p(0) and cin); 
	---computation of sum
	sum <= p xor c;
end architecture;

Testbench

• Código
• Resultado (print)

Simulações

Nº Bits	ALMs	Delay	Potência (mW)
x	x	x	x
x	x	x	x
x	x	x	x
x	x	x	x