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Estrutura
Código VHDL
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
entity deserial is
GENERIC (bits : INTEGER := 3; -- Bits do contador interno log2(n)
n : INTEGER := 8 -- Dados seriais transmitidos
);
PORT
(
din : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
areset : IN STD_LOGIC;
locked : OUT STD_LOGIC;
doutS : OUT STD_LOGIC;
count_outD : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
count_outS : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
doutD : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
);
END entity;
ARCHITECTURE bdf_type OF deserial IS
COMPONENT fast_deserializer
GENERIC (bits : INTEGER;
n : INTEGER
);
PORT(clk : IN STD_LOGIC;
din : IN STD_LOGIC;
count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT fast_serializer
GENERIC (bits : INTEGER;
n : INTEGER
);
PORT(clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
dout : OUT STD_LOGIC;
count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT altpll0
PORT(inclk0 : IN STD_LOGIC;
areset : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
locked : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL s_clk : STD_LOGIC;
SIGNAL deserial_data : STD_LOGIC_VECTOR(n-1 DOWNTO 0);
--Keep
attribute keep: boolean;
attribute keep of deserial_data: signal is true;
BEGIN
doutD <= deserial_data;
deserial_inst : fast_deserializer
GENERIC MAP(bits => bits,
n => n
)
PORT MAP(clk => s_clk,
din => din,
count_out => count_outD,
dout => deserial_data);
serial_inst : fast_serializer
GENERIC MAP(bits => bits,
n => n
)
PORT MAP(clk => s_clk,
din => deserial_data,
dout => doutS,
count_out => count_outS);
pll0_inst : altpll0
PORT MAP(inclk0 => inclk0,
areset => areset,
c0 => s_clk,
locked => locked);
END architecture;
Testbench
Simulações
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ALMs
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Delay
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