Mudanças entre as edições de "Circuito Deserializador - Pedroni VHDL"

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__NOTOC__
 
__NOTOC__
 
==Estrutura==
 
==Estrutura==
−
*
+
*Circuito deserializador (Recebe logic, sai logic_vector)
−
*
+
*Possui um contador de teste afim de depuração (Exemplo do Loop: conta até 3 e joga o bit que está na entrada ṕara a saída.)
  
−
==Código VHDL==
+
==VHDL==
 +
{{Collapse top | Código}}
 
<syntaxhighlight lang=vhdl>
 
<syntaxhighlight lang=vhdl>
−
LIBRARY ieee;
+
library ieee;
−
USE ieee.std_logic_1164.all;  
+
use ieee.std_logic_1164.all;
 +
use ieee.numeric_std.all;
  
−
LIBRARY work;
+
entity fast_deserializer is
  
−
entity deserial is
+
generic (n: integer := 4; bits : integer :=2);
 +
port(
 +
clk: in std_logic;
 +
din: in std_logic;
 +
count_out: out std_logic_vector(bits-1 downto 0);  -- so para depuracao
 +
--sclk_teste: out std_logic;
 +
dout: out std_logic_vector (n-1 downto 0));
 +
end entity;
 +
 +
architecture fast_deserializer of fast_deserializer is
 +
 +
begin
  
−
GENERIC (bits : INTEGER := 3;  -- Bits do contador interno log2(n)
+
process(clk)
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n : INTEGER := 8 -- Dados seriais transmitidos
+
variable count : integer range 0 to n := 0;
−
);
+
variable internal: std_logic_vector (n-1 downto 0);
−
PORT
+
begin
−
(
+
if(rising_edge(clk)) then
−
din : IN  STD_LOGIC;
+
internal(count) := din;  
−
inclk0 :  IN  STD_LOGIC;
+
count_out <= std_logic_vector(to_unsigned(count, bits));
−
areset :  IN  STD_LOGIC;
+
count := count +1;
−
locked :  OUT  STD_LOGIC;
+
if (count= n) then --enable to update "internal"
−
doutS :  OUT  STD_LOGIC;
+
dout <= internal;
−
count_outD :  OUT  STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
+
count := 0;
−
count_outS : OUT  STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
+
end if;
−
doutD : OUT  STD_LOGIC_VECTOR(n-1 DOWNTO 0)
+
end if;
−
);
+
−
END entity;
+
end process;
−
 
+
end architecture;
−
ARCHITECTURE bdf_type OF deserial IS
+
 
−
 
+
</syntaxhighlight>
−
COMPONENT fast_deserializer
+
{{Collapse bottom}}
−
GENERIC (bits : INTEGER; 
 
−
n : INTEGER
 
−
);
 
−
PORT(clk : IN STD_LOGIC;
 
−
din : IN STD_LOGIC;
 
−
count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
 
−
dout : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
 
−
);
 
−
END COMPONENT;
 
−
 
 
−
COMPONENT fast_serializer
 
−
GENERIC (bits : INTEGER; 
 
−
n : INTEGER
 
−
);
 
−
PORT(clk : IN STD_LOGIC;
 
−
din : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
 
−
dout : OUT STD_LOGIC;
 
−
count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0)
 
−
);
 
−
END COMPONENT;
 
−
 
 
−
COMPONENT altpll0
 
−
PORT(inclk0 : IN STD_LOGIC;
 
−
areset : IN STD_LOGIC;
 
−
c0 : OUT STD_LOGIC;
 
−
locked : OUT STD_LOGIC
 
−
);
 
−
END COMPONENT;
 
−
 
 
−
SIGNAL s_clk :  STD_LOGIC;
 
−
SIGNAL deserial_data :  STD_LOGIC_VECTOR(n-1 DOWNTO 0);
 
−
 
 
−
--Keep
 
−
attribute keep: boolean;
 
−
attribute keep of deserial_data: signal is true;
 
−
 
 
−
BEGIN
 
−
 
 
−
doutD <= deserial_data;
 
−
 
 
−
 
 
−
deserial_inst : fast_deserializer
 
−
GENERIC MAP(bits => bits,
 
−
n => n
 
−
)
 
−
PORT MAP(clk => s_clk,
 
−
din => din,
 
−
count_out => count_outD,
 
−
dout => deserial_data);
 
−
 
 
−
 
 
−
serial_inst : fast_serializer
 
−
GENERIC MAP(bits => bits,
 
−
n => n
 
−
)
 
−
PORT MAP(clk => s_clk,
 
−
din => deserial_data,
 
−
dout => doutS,
 
−
count_out => count_outS);
 
  
 +
==Testbench==
 +
{{Collapse top | Código}}
 +
<syntaxhighlight lang=vhdl>
  
−
pll0_inst : altpll0
 
−
PORT MAP(inclk0 => inclk0,
 
−
areset => areset,
 
−
c0 => s_clk,
 
−
locked => locked);
 
−
 
−
 
−
END architecture;
 
−
 
 
 
</syntaxhighlight>
 
</syntaxhighlight>
 +
{{Collapse bottom}}
  
−
==Testbench==
+
*Resultado Funcional:
−
*Código
+
[[Arquivo: .png | 200px]]
−
*Resultado (print)
+
*Resultado Temporal:
 +
[[Arquivo: .png | 200px]]
  
 
==Simulações==
 
==Simulações==

Edição das 11h00min de 29 de março de 2016

Estrutura

  • Circuito deserializador (Recebe logic, sai logic_vector)
  • Possui um contador de teste afim de depuração (Exemplo do Loop: conta até 3 e joga o bit que está na entrada ṕara a saída.)

VHDL

Código 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fast_deserializer is

	generic (n: integer := 4; bits : integer :=2);
	port(
		clk: in std_logic;
		din: in std_logic;
		count_out: out std_logic_vector(bits-1 downto 0);  -- so para depuracao
		--sclk_teste: out std_logic;
		dout: out std_logic_vector (n-1 downto 0));
end entity;
	
architecture fast_deserializer of fast_deserializer is
	
begin

	process(clk)
		variable count : integer range 0 to n := 0;
		variable internal: std_logic_vector (n-1 downto 0);
		begin	
			if(rising_edge(clk)) then
				internal(count) := din; 
				count_out <= std_logic_vector(to_unsigned(count, bits));
				count := count +1;
				if (count= n) then --enable to update "internal"
					dout <= internal;
					count := 0;
				end if;
			end if;
			
	end process;
end architecture;

Testbench

Código
  • Resultado Funcional:

200px

  • Resultado Temporal:

200px

Simulações

Nº Bits ALMs Delay Potência (mW)
x x x x
x x x x
x x x x
x x x x
Disponível em “https://wiki.sj.ifsc.edu.br/index.php?title=Circuito_Deserializador_-_Pedroni_VHDL&oldid=103980”