Carry Skip

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--Book: Arithmetic/294
-- Carry skip

architecture adder_carry_skip of adder is

component carry_skip
	generic (n: natural := 4;
				m : natural := 1;
				k : natural := 4 
				);
	port 
		(a, b: in std_logic_vector(k-1 downto 0);
		cin: in std_logic;
		c_out: out std_logic_vector(k downto 1)
		);
end component;

	
	constant mb: natural := 2;
	subtype digit is natural range 0 to mb-1;
	type digit_vector is array (natural range <>) of digit;
	
	signal q: std_logic_vector(n downto 0);
	signal s_a, s_b: digit_vector(n-1 downto 0);
	signal z: digit_vector(n-1 downto 0);

begin
	conv_dv2slv: for i in s_a'range generate
		s_a(i) <= 1 when a(i)='1' else 0;
		s_b(i) <= 1 when b(i)='1' else 0;
		sum(i) <= '1' when z(i)=1 else '0';
	end generate;
	
q(0) <= cin;

ext_iteration: for i in 0 to m-1 generate
carry_chain: carry_skip 
	port map(
			a(i*k+k-1 downto i*k), 
			b(i*k+k-1 downto i*k), 
			q(i*k),
			q(i*k+k downto i*k+1));
			
		int_iteration: for j in 0 to k-1 generate 

		z(i*k+j) <= (s_a(i*k+j) + s_b(i*k+j) + conv_integer(q(i*k+j))) mod mb; 
		end generate;
	end generate;
--c_out <= q(n);
end architecture;