Mudanças entre as edições de "Carry Skip"
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(Criou página com '<syntaxhighlight lang=vhdl> ------------------------------------------------------------------------------------------ ---------------------------------------------------------------------------...') |
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Linha 52: | Linha 52: | ||
--c_out <= q(n); | --c_out <= q(n); | ||
end architecture; | end architecture; | ||
+ | |||
+ | ------------------------------------------------------------------- | ||
+ | library ieee; | ||
+ | use ieee.std_logic_1164.all; | ||
+ | use ieee.std_logic_arith.all; | ||
+ | use ieee.std_logic_unsigned.all; | ||
+ | |||
+ | entity carry_skip is | ||
+ | generic (k : natural; | ||
+ | m : natural); | ||
+ | port | ||
+ | (a_in, b_in: in std_logic_vector(k-1 downto 0); | ||
+ | cin: in std_logic; | ||
+ | c_out: out std_logic_vector(k downto 1) | ||
+ | ); | ||
+ | end carry_skip; | ||
+ | |||
+ | architecture circuit of carry_skip is | ||
+ | |||
+ | constant mb: natural := 2; | ||
+ | subtype digit is natural range 0 to mb-1; | ||
+ | type digit_vector is array (natural range <>) of digit; | ||
+ | |||
+ | signal p, g: std_logic_vector(k-1 downto 0); | ||
+ | signal generalized_p: std_logic; | ||
+ | signal q: std_logic_vector(k downto 0); | ||
+ | signal s_a, s_b: digit_vector(k-1 downto 0); | ||
+ | |||
+ | begin | ||
+ | |||
+ | conv_dv2slv: for i in s_a'range generate | ||
+ | s_a(i) <= 1 when a_in(i)='1' else 0; | ||
+ | s_b(i) <= 1 when b_in(i)='1' else 0; | ||
+ | end generate; | ||
+ | q(0) <= cin; | ||
+ | |||
+ | iterative_step: for i in 0 to k-1 generate | ||
+ | p(i) <= '1' when s_a(i) + s_b(i) = mb-1 else '0'; | ||
+ | g(i) <= '1' when s_a(i) + s_b(i) > mb-1 else'0'; | ||
+ | with p(i) select q(i+1) <= q(i) when '1', g(i) when others; | ||
+ | end generate; | ||
+ | |||
+ | process(p) | ||
+ | variable accumulator: std_logic; | ||
+ | begin | ||
+ | accumulator := p(0); | ||
+ | for i in 1 to k-1 loop accumulator := accumulator and p(i); | ||
+ | end loop; | ||
+ | generalized_p <= accumulator; | ||
+ | end process; | ||
+ | |||
+ | with generalized_p select c_out(k) <= cin when '1', q(k) when others; | ||
+ | |||
+ | carries: for i in 1 to k-1 generate | ||
+ | c_out(i) <= q(i); | ||
+ | end generate; | ||
+ | |||
+ | end architecture; | ||
</syntaxhighlight> | </syntaxhighlight> |
Edição atual tal como às 21h59min de 31 de agosto de 2016
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--Book: Arithmetic/294
-- Carry skip
architecture adder_carry_skip of adder is
component carry_skip
generic (n: natural := 4;
m : natural := 1;
k : natural := 4
);
port
(a, b: in std_logic_vector(k-1 downto 0);
cin: in std_logic;
c_out: out std_logic_vector(k downto 1)
);
end component;
constant mb: natural := 2;
subtype digit is natural range 0 to mb-1;
type digit_vector is array (natural range <>) of digit;
signal q: std_logic_vector(n downto 0);
signal s_a, s_b: digit_vector(n-1 downto 0);
signal z: digit_vector(n-1 downto 0);
begin
conv_dv2slv: for i in s_a'range generate
s_a(i) <= 1 when a(i)='1' else 0;
s_b(i) <= 1 when b(i)='1' else 0;
sum(i) <= '1' when z(i)=1 else '0';
end generate;
q(0) <= cin;
ext_iteration: for i in 0 to m-1 generate
carry_chain: carry_skip
port map(
a(i*k+k-1 downto i*k),
b(i*k+k-1 downto i*k),
q(i*k),
q(i*k+k downto i*k+1));
int_iteration: for j in 0 to k-1 generate
z(i*k+j) <= (s_a(i*k+j) + s_b(i*k+j) + conv_integer(q(i*k+j))) mod mb;
end generate;
end generate;
--c_out <= q(n);
end architecture;
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity carry_skip is
generic (k : natural;
m : natural);
port
(a_in, b_in: in std_logic_vector(k-1 downto 0);
cin: in std_logic;
c_out: out std_logic_vector(k downto 1)
);
end carry_skip;
architecture circuit of carry_skip is
constant mb: natural := 2;
subtype digit is natural range 0 to mb-1;
type digit_vector is array (natural range <>) of digit;
signal p, g: std_logic_vector(k-1 downto 0);
signal generalized_p: std_logic;
signal q: std_logic_vector(k downto 0);
signal s_a, s_b: digit_vector(k-1 downto 0);
begin
conv_dv2slv: for i in s_a'range generate
s_a(i) <= 1 when a_in(i)='1' else 0;
s_b(i) <= 1 when b_in(i)='1' else 0;
end generate;
q(0) <= cin;
iterative_step: for i in 0 to k-1 generate
p(i) <= '1' when s_a(i) + s_b(i) = mb-1 else '0';
g(i) <= '1' when s_a(i) + s_b(i) > mb-1 else'0';
with p(i) select q(i+1) <= q(i) when '1', g(i) when others;
end generate;
process(p)
variable accumulator: std_logic;
begin
accumulator := p(0);
for i in 1 to k-1 loop accumulator := accumulator and p(i);
end loop;
generalized_p <= accumulator;
end process;
with generalized_p select c_out(k) <= cin when '1', q(k) when others;
carries: for i in 1 to k-1 generate
c_out(i) <= q(i);
end generate;
end architecture;