Carry Lookahead 4 bits

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--Book: Eletronica digital moderna e VHDL/490
-- Carry lookahead com 4 bits

architecture adder_carry_lookahead_4 of adder is

	signal carry: std_logic_vector(n/4 downto 0); 
	
	component carry_lookahead_adder_4 is
			port( a,b : in std_logic_vector(3 downto 0);
			cin: in std_logic;
			cout: out std_logic;
			sum: out std_logic_vector(3 downto 0));
	end component;
	
begin
	carry(0) <= cin;
	gen_adder: for i in 1 to n/4 generate
		adder: carry_lookahead_adder_4 
			port map(
				a => a(4*i-1 downto 4*i-4),
				b => b(4*i-1 downto 4*i-4),
				cin => carry(i-1),
				sum => sum(4*i-1 downto 4*i-4),
				cout => carry(i)
			);
		end generate;
		
end architecture;