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(Criou página com '<syntaxhighlight lang=vhdl> LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; entity DUT_adder is GENERIC (n_DUT : INTEGER := 4; -- Dados seriais transmitidos bits_DUT : INTEGER :=...') |
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Edição atual tal como às 11h05min de 3 de julho de 2016
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
entity DUT_adder is
GENERIC (n_DUT : INTEGER := 4; -- Dados seriais transmitidos
bits_DUT : INTEGER := 2; -- Bits do contador interno log2(n)
k_DUT : integer := 4;
m_DUT : integer := 1
);
PORT
(
inclk0 : IN STD_LOGIC;
din0 : IN STD_LOGIC;
din1 : IN STD_LOGIC;
cin : in std_lOGIC;
doutS : OUT STD_LOGIC;
sum_DUT: OUT STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0)
-- PARA DEPUARAAO --RETIRAR PARA MEDIR DESEMPENHO
);
END entity;
ARCHITECTURE dut OF DUT_adder IS
COMPONENT fast_deserializer
GENERIC (bits : INTEGER;
n : INTEGER
);
PORT(clk : IN STD_LOGIC;
din : IN STD_LOGIC;
count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT fast_serializer
GENERIC (bits : INTEGER;
n : INTEGER
);
PORT(clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
dout : OUT STD_LOGIC;
count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT adder
GENERIC (n : INTEGER;
m : integer;
k: integer
);
PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
cin: IN std_LOGIC;
sum : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL s_clk, s_cin : STD_LOGIC;
SIGNAL deserial_data0: STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
SIGNAL deserial_data1: STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
SIGNAL saida: STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0) := (others => '0');
-- Para preservar os sinais dos barramentos de entrada e saida do DUT
attribute keep : boolean;
attribute keep of s_cin, deserial_data0, deserial_data1, saida : signal is TRUE;
BEGIN
sum_DUT <= saida;
s_clk <= inclk0;
s_cin <= cin;
inst_deserial0 : fast_deserializer
GENERIC MAP(bits => bits_DUT,
n => n_DUT
)
PORT MAP(clk => s_clk,
din => din0,
count_out => open,
dout => deserial_data0);
inst_serial : fast_serializer
GENERIC MAP(bits => bits_DUT,
n => n_DUT
)
PORT MAP(clk => s_clk,
din => saida,
dout => doutS,
count_out => open);
inst_deserial1 : fast_deserializer
GENERIC MAP(bits => bits_DUT,
n => n_DUT
)
PORT MAP(clk => s_clk,
din => din1,
count_out => open,
dout => deserial_data1);
--inst_adder : entity work.adder(adder_stub) -- Stub sem somador
--inst_adder : entity work.adder(adder) -- operador de soma (+) do VHDL
--inst_adder : entity work.adder(adder_carry_ripple) -- Carry ripple portas
--inst_adder : entity work.adder(adder_carry_select) -- Carry select
--inst_adder : entity work.adder(adder_carry_chain) -- Carry chain
--inst_adder : entity work.adder(adder_carry_skip) -- Carry skip
--inst_adder : entity work.adder(adder_carry_lookahead_4) -- Carry lookahead portas 4 bits
--inst_adder : entity work.adder(adder_carry_lookahead_8) -- Carry lookahead portas 8 bits
--inst_adder : entity work.adder(adder_carry_lookahead_16) -- Carry lookahead portas 16 bits
GENERIC MAP(n => n_DUT,
m => m_DUT,
k => k_DUT
)
PORT MAP(a => deserial_data0,
b => deserial_data1,
cin => s_cin,
sum => saida);
END ARCHITECTURE;