Circuito Multiplicador - Guide
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Estrutura
Código VHDL
----------------------------------------------------------------------------
-- parallel_csa_multiplier.vhd
--
-- section 8.2.2 parallel carry save adder(CSA) multiplier
--
-- Computes: z = x·y + u + v
-- x, u: n bits
-- y, v: m bits
-- z: n+m bits
-- for n greater than or equal to m
--
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY parallel_csa_multiplier IS
GENERIC(n: NATURAL:= 8; m: NATURAL:= 8);
PORT(
x, u: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
y, v: IN STD_LOGIC_VECTOR(m-1 DOWNTO 0);
z: OUT STD_LOGIC_VECTOR(n+m-1 DOWNTO 0)
);
END parallel_csa_multiplier;
ARCHITECTURE circuit OF parallel_csa_multiplier IS
TYPE matrix IS ARRAY (0 TO m-1) OF STD_LOGIC_VECTOR(n-1 DOWNTO 0);
SIGNAL c, d, e, f: matrix;
SIGNAL first_operand: STD_LOGIC_VECTOR(n-2 DOWNTO 0);
SIGNAL second_operand: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
BEGIN
main_iteration: FOR i IN 0 TO m-1 GENERATE
internal_iteration: FOR j IN 0 TO n-1 GENERATE
f(i)(j) <= (x(j) AND y(i)) XOR c(i)(j) XOR d(i)(j);
e(i)(j) <= (x(j) AND y(i) AND c(i)(j)) OR (x(j) AND y(i) AND d(i)(j)) OR (c(i)(j) AND d(i)(j));
END GENERATE;
END GENERATE;
connections1: FOR j IN 0 TO n-1 GENERATE
c(0)(j) <= u(j);
END GENERATE;
connections2: FOR i IN 1 TO m-1 GENERATE
connections3: FOR j IN 0 TO n-2 GENERATE
c(i)(j) <= f(i-1)(j+1);
END GENERATE;
c(i)(n-1) <= '0';
END GENERATE;
connections4: FOR j IN 0 TO m-1 GENERATE
d(0)(j) <= v(j);
END GENERATE;
connections5: FOR j IN m TO n-1 GENERATE
d(0)(j) <= '0';
END GENERATE;
connections6: FOR i IN 1 TO m-1 GENERATE
connections7: FOR j IN 0 TO n-1 GENERATE
d(i)(j) <= e(i-1)(j);
END GENERATE;
END GENERATE;
outputs: FOR j IN 0 TO m-1 GENERATE
z(j) <= f(j)(0);
END GENERATE;
first_operand<= f(m-1)(n-1 DOWNTO 1);
second_operand <= e(m-1);
z(n+m-1 DOWNTO m) <= first_operand + second_operand;
END circuit;
----------------------------------------------------------------------------
-- integer_csa_multiplier.vhd
--
-- section 8.4.1 parallel carry save adder(CSA) multiplier for integer numbers
--
-- Computes: z = x·y + u + v
-- x, u: n+1 bits
-- y, v: m+1 bits
-- z: n+m+1 bits
-- for n greater than or equal to m
--
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY integer_csa_multiplier IS
GENERIC(n: NATURAL:= 32; m: NATURAL:= 32);
PORT(
x, u: IN STD_LOGIC_VECTOR(n DOWNTO 0);
y, v: IN STD_LOGIC_VECTOR(m DOWNTO 0);
z: OUT STD_LOGIC_VECTOR(n+m+1 DOWNTO 0)
);
END integer_csa_multiplier;
ARCHITECTURE circuit OF integer_csa_multiplier IS
COMPONENT parallel_csa_multiplier IS
GENERIC(n, m: NATURAL);
PORT(
x, u: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
y, v: IN STD_LOGIC_VECTOR(m-1 DOWNTO 0);
z: OUT STD_LOGIC_VECTOR(n+m-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL long_x, long_y, long_u, long_v: STD_LOGIC_VECTOR(n+m+1 DOWNTO 0);
SIGNAL long_z: STD_LOGIC_VECTOR(2*n+2*m+3 DOWNTO 0);
BEGIN
long_x(n+m+1 DOWNTO n+1) <= (OTHERS => x(n)); long_x(n DOWNTO 0) <= x;
long_u(n+m+1 DOWNTO n+1) <= (OTHERS => u(n)); long_u(n DOWNTO 0) <= u;
long_y(n+m+1 DOWNTO m+1) <= (OTHERS => y(m)); long_y(m DOWNTO 0) <= y;
long_v(n+m+1 DOWNTO m+1) <= (OTHERS => v(m)); long_v(m DOWNTO 0) <= v;
main_component: parallel_csa_multiplier GENERIC MAP(n => n+m+2, m => n+m+2)
PORT MAP(x => long_x, u => long_u, y => long_y, v => long_v, z => long_z);
z <= long_z(n+m+1 DOWNTO 0);
END circuit;
Testbench
- Código
- Resultado (print)
Simulações
Nº Bits | ALMs | Delay | Potência (mW) |
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x | x | x | x |
x | x | x | x |
x | x | x | x |
x | x | x | x |