Circuito Multiplicador - Pedroni-VHDL
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Estrutura
Código VHDL
--Book: PedroniVHDL/77
--4 bits
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all; --for arch1
--USE ieee.std_logic_arith.all; --for arch2, arch3
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ENTITY signed_multiplier IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
prod: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;
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ARCHITECTURE arch1 OF signed_multiplier IS
SIGNAL a_sig, b_sig: SIGNED(3 DOWNTO 0);
BEGIN
a_sig <= SIGNED(a);
b_sig <= SIGNED(b);
prod <= STD_LOGIC_VECTOR(a_sig * b_sig);
END arch1;
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-- ARCHITECTURE arch2 OF signed_multiplier IS
-- SIGNAL a_sig, b_sig: SIGNED(3 DOWNTO 0);
-- SIGNAL prod_sig: SIGNED(7 DOWNTO 0);
-- BEGIN
-- a_sig <= SIGNED(a);
-- b_sig <= SIGNED(b);
-- prod_sig <= a_sig * b_sig;
-- prod <= STD_LOGIC_VECTOR(prod_sig);
-- END arch2;
-- ----------------------------------------------------
-- ARCHITECTURE arch3 OF signed_multiplier IS
-- SIGNAL a_sig, b_sig: SIGNED(3 DOWNTO 0);
-- BEGIN
-- a_sig <= SIGNED(a);
-- b_sig <= SIGNED(b);
-- prod <= STD_LOGIC_VECTOR(SIGNED'(a_sig * b_sig));
-- END arch3;
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Testbench
- Código
- Resultado (print)
Simulações
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