Arranjo de Multiplicadores - John
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Estrutura
Código VHDL
--Book: John/218
--4 bits
library ieee;
use ieee.numeric_bit.all;
entity array_mult is
port(
x,y : in bit_vector(3 downto 0);
p: out bit_vector(7 downto 0));
end entity;
architecture array_mult of array_mult is
signal c1,c2,c3 : bit_vector(3 downto 0);
signal s1,s2,s3 : bit_vector(3 downto 0);
signal xy0,xy1,xy2,xy3: bit_vector(3 downto 0);
component fulladder
port(
x,y, cin: in bit;
cout, sum: out bit);
end component;
component halfadder
port(
x,y: in bit;
cout, sum: out bit);
end component;
begin
xy0(0) <= x(0) and y(0);
xy0(1) <= x(1) and y(0);
xy0(2) <= x(2) and y(0);
xy0(3) <= x(3) and y(0);
xy1(0) <= x(0) and y(1);
xy1(1) <= x(1) and y(1);
xy1(2) <= x(2) and y(1);
xy1(3) <= x(3) and y(1);
xy2(0) <= x(0) and y(2);
xy2(1) <= x(1) and y(2);
xy2(2) <= x(2) and y(2);
xy2(3) <= x(3) and y(2);
xy3(0) <= x(0) and y(3);
xy3(1) <= x(1) and y(3);
xy3(2) <= x(2) and y(3);
xy3(3) <= x(3) and y(3);
fa1: fulladder port map (xy0(2), xy1(1), c1(0), c1(1), s1(1));
fa2: fulladder port map (xy0(3), xy1(2), c1(1), c1(2), s1(2));
fa3: fulladder port map (s1(2), xy2(1), c2(0), c2(1), s2(1));
fa4: fulladder port map (s1(3), xy2(2), c2(1), c2(2), s2(2));
fa5: fulladder port map (c1(3), xy2(3), c2(2), c2(3), s2(3));
fa6: fulladder port map (s2(2), xy3(1), c3(0), c3(1), s3(1));
fa7: fulladder port map (s2(3), xy3(2), c3(1), c3(2), s3(2));
fa8: fulladder port map (c2(3), xy3(3), c3(2), c3(3), s3(3));
ha1: halfadder port map (xy0(1), xy1(0), c1(0), s1(0));
ha2: halfadder port map (xy1(3), c1(2), c1(3), s1(3));
ha3: halfadder port map (s1(1), xy2(0), c2(0), s2(0));
ha4: halfadder port map (s2(1), xy3(0), c3(0), s3(0));
p(0) <= xy0(0);
p(1) <= s1(0);
p(2) <= s2(0);
p(3) <= s3(0);
p(4) <= s3(1);
p(5) <= s3(2);
p(6) <= s3(3);
p(7) <= c3(3);
end architecture;
Testbench
- Código
- Resultado (print)
Simulações
Nº Bits | ALMs | Delay | Potência (mW) |
---|---|---|---|
x | x | x | x |
x | x | x | x |
x | x | x | x |
x | x | x | x |