Operador de multiplicação VHDL

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--Book: Circuit design/ 77
--Multiplicador sem sinal

architecture multiplier_unsigned of multiplier is

	signal a_sig, b_sig: unsigned(n-1 downto 0);
		 
	begin
		 a_sig <= unsigned(a);
		 b_sig <= unsigned(b);
		 prod <= std_logic_vector(unsigned' (a_sig * b_sig));
		 
end architecture;