Operador VHDL
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--Book: Circuit design/ 140
--Somador com operador sem sinal
architecture adder of adder is
signal sum_sig : unsigned (n-1 downto 0);
begin
--Convert to signed and add_sub
sum_sig <= unsigned(a) + unsigned(b);
--Return to std_logic_vector
sum <= std_logic_vector (sum_sig);
end architecture;