Carry Ripple
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--Book: Circuit design/ 164
-- Carry-ripple
architecture adder_carry_ripple of adder is
begin
process (a,b, cin)
variable carry: std_logic_vector (n downto 0);
begin
carry(0) := cin;
for i in 0 to n-1 loop
sum(i) <= a(i) xor b(i) xor carry(i);
carry(i+1) := (a(i) and b(i)) or (a(i) and carry(i)) or (b(i) and carry(i));
end loop;
--cout <= carry(n);
end process;
end architecture;