Como evitar o uso da lógica combinacional no reset síncrono
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Para evitar o uso do circuito combinacional para a entrada CLEAR_SYNC no flip_flop D é necessário utilizar a Low-Level Primitives DFFEAS
library ieee;
use ieee.std_logic_1164.all;
entity FF_D is
port
(
clock : in STD_LOGIC;
sync_clr : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC := '0');
end entity;
architecture ifsc of FF_D is
component DFFEAS
port
(
d : in STD_LOGIC;
clk : in STD_LOGIC;
clrn : in STD_LOGIC;
prn : in STD_LOGIC;
ena : in STD_LOGIC;
asdata : in STD_LOGIC;
aload : in STD_LOGIC;
sclr : in STD_LOGIC;
sload : in STD_LOGIC;
q : out STD_LOGIC);
end component;
begin
FFD : DFFEAS
port map
(
d => d,
clk => clock,
clrn => '1',
prn => '1',
ena => '1',
asdata => '0',
aload => '0',
sclr => sync_clr,
sload => '0',
q => q);
end architecture;
Figura 1 - RTL de Flip-flop D com reset síncrono
Figura 2 - Technology map de Flip-flop D com reset síncrono
- Ler
- Designing with Low-Level Primitives User Guide pag.2–28 - Altera Corporation 2007