Subtractor

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

entity DUT_sub is

GENERIC (bits_DUT : INTEGER := 5;  -- Bits do contador interno log2(n)
			n_DUT : INTEGER :=  32  -- Dados seriais transmitidos
			);
	PORT
	(
		inclk0 :  IN  STD_LOGIC;
		din0 :  IN  STD_LOGIC;
		din1 :  IN  STD_LOGIC;
		bin	: in std_lOGIC;
		doutS :  OUT  STD_LOGIC;
		sub_DUT: OUT STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0) 
		-- PARA DEPUARAAO  --RETIRAR PARA MEDIR DESEMPENHO
	);
END entity;

ARCHITECTURE dut OF DUT_sub IS 

COMPONENT fast_deserializer
GENERIC (bits : INTEGER;
			n : INTEGER
			);
	PORT(clk : IN STD_LOGIC;
		 din : IN STD_LOGIC;
		 count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
		 dout : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
	);
END COMPONENT;

COMPONENT fast_serializer
GENERIC (bits : INTEGER;
			n : INTEGER
			);
	PORT(clk : IN STD_LOGIC;
		 din : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
		 dout : OUT STD_LOGIC;
		 count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0)
	); 
END COMPONENT;

component subtractor is
	
	generic (n: natural := 4);
	port(
		a,b: in std_logic_vector (n-1 downto 0);
		sub : out std_logic_vector (n-1 downto 0));
end component;
 
	SIGNAL	s_clk, s_bin :  STD_LOGIC;
	SIGNAL	deserial_data0:  STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
	SIGNAL	deserial_data1:  STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
	SIGNAL	saida:  STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
	
	--	Para preservar os sinais dos barramentos de entrada e saida do DUT
	attribute keep : boolean;
	attribute keep of s_bin, deserial_data0, deserial_data1, saida : signal is TRUE;


BEGIN 

sub_DUT <= saida;
s_clk <= inclk0;
s_bin <= bin;

	inst_deserial0 : fast_deserializer
		GENERIC MAP(bits => bits_DUT,
					n => n_DUT
					)
		PORT MAP(clk => s_clk,
				 din => din0,
				 count_out => open,
				 dout => deserial_data0);

	inst_serial : fast_serializer
		GENERIC MAP(bits => bits_DUT,
					n => n_DUT
					)
		PORT MAP(clk => s_clk,
				 din => saida,
				 dout => doutS,
				 count_out => open);

	inst_deserial1 : fast_deserializer
		GENERIC MAP(bits => bits_DUT,
					n => n_DUT
					)
		PORT MAP(clk => s_clk,
				 din => din1,
				 count_out => open,
				 dout => deserial_data1);


	--inst_sub : entity work.subtractor(sub_stub)  	-- Stub sem subtrator
	inst_sub : entity work.subtractor(subtractor)  	-- Sub utilizando o operador de subtracao (-) do VHDL
	--inst_sub : entity work.subtractor(compl2)  ---Complemento de 2
	
		GENERIC MAP(n => n_DUT
				)
		PORT MAP(a => deserial_data0,
			 b => deserial_data1,
			 bin => s_bin,
			 sub => saida);


END ARCHITECTURE;