Multiplier

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
LIBRARY work;

entity DUT_mult is      
	GENERIC (n_DUT : INTEGER := 32; -- Dados seriais transmitidos
				bits_DUT : INTEGER := 5  -- Bits do contador interno log2(n)
			);
	PORT
	(
		inclk0 :  IN  STD_LOGIC;
		din0 :  IN  STD_LOGIC;
		din1 :  IN  STD_LOGIC;
		cin	: in std_lOGIC;
		doutS :  OUT  STD_LOGIC;
		prod_DUT: OUT STD_LOGIC_VECTOR(2*n_DUT-1 DOWNTO 0) 
		-- PARA DEPUARAAO  --RETIRAR PARA MEDIR DESEMPENHO
	);
END entity;

ARCHITECTURE dut OF DUT_mult IS 

	COMPONENT fast_deserializer
	GENERIC (bits : INTEGER;
				n : INTEGER
				);
		PORT(clk : IN STD_LOGIC;
			 din : IN STD_LOGIC;
			 count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
			 dout : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
		);
	END COMPONENT;

	COMPONENT fast_serializer
	GENERIC (bits : INTEGER;
				n : INTEGER
				);
		PORT(clk : IN STD_LOGIC;
			 din : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
			 dout : OUT STD_LOGIC;
			 count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0)
		); 
	END COMPONENT;

	component multiplier IS
		
		generic (n: natural);
		 PORT 
		 (a, b: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
		 cin : std_logic_vector(n-1 DOWNTO 0);
		 prod: OUT STD_LOGIC_VECTOR(2*n-1 DOWNTO 0));
	END component;
 
 
	SIGNAL	s_clk:  STD_LOGIC;
	signal   s_cin:  std_logic_vector(n_DUT-1 downto 0);
	SIGNAL	deserial_data0:  STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
	SIGNAL	deserial_data1:  STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
	SIGNAL	saida:  STD_LOGIC_VECTOR(2*n_DUT-1 DOWNTO 0);
	
	--	Para preservar os sinais dos barramentos de entrada e saida do DUT
	attribute keep : boolean;
	attribute keep of s_cin, deserial_data0, deserial_data1, saida : signal is TRUE;

BEGIN 

--	s_cin <= cin;
	s_clk <= inclk0;
	prod_DUT <= saida;

	inst_deserial0 : fast_deserializer
	GENERIC MAP(bits => bits_DUT,
				n => n_DUT
				)
	PORT MAP(clk => s_clk,
			 din => din0,
			 count_out => open,
			 dout => deserial_data0);
			 
	inst_deserial1 : fast_deserializer
	GENERIC MAP(bits => bits_DUT,
				n => n_DUT
				)
	PORT MAP(clk => s_clk,
			 din => din1,
			 count_out => open,
			 dout => deserial_data1);
			 
	inst_deserial_cin : fast_deserializer
	GENERIC MAP(bits => bits_DUT,
				n => n_DUT
				)
	PORT MAP(clk => s_clk,
			 din => cin,
			 count_out => open,
			 dout => s_cin);		 
			 

	inst_serial : fast_serializer
	GENERIC MAP(bits => bits_DUT+1,
				n => 2*n_DUT
				)
	PORT MAP(clk => s_clk,
			 din => saida,
			 dout => doutS,
			 count_out => open);

	--inst_mult : entity work.multiplier(multiplier_stub)     			-- Stub sem multiplier
	--inst_mult : entity work.multiplier(multiplier_unsigned)   		-- Multiplicacao sem sinal (operador)
	inst_mult : entity work.multiplier(carry_save_mult)  	       	-- Carry save multiplier	
	--inst_mult : entity work.multiplier(ripple_carry_mult)  	   	-- Ripple multiplier	
	
	
	GENERIC MAP(n => n_DUT)
	PORT MAP(a => deserial_data0,
			b => deserial_data1,
			cin	=> s_cin,
			prod => saida);

END ARCHITECTURE;