Circuito Somador e Subtrator 2 - Chu

Código VHDL

--Book: Chu/171
--8 bits
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity addsub is 
	port( a,b: in std_logic_vector (7 downto 0);
			ctrl: in std_logic;
			r: out std_logic_vector(7 downto 0));
			
end entity;

architecture direct_Arch of addsub is
	signal src0, src1, sum: signed (7 downto 0);
	signal cin: signed(0 downto 0); 
	
begin
	src0 <= signed(a);
	src1 <= signed(b) when ctrl='0' else	
			  signed(not b);
	cin <= "0" when ctrl='0' else
			 "1";
	sum <= src0 + src1 + cin;	
	r <= std_logic_vector(sum);
	
end architecture;

Testbench

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Simulações

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