Circuito Somador BCD - John

Código VHDL

--Book: John/194
--8 bits
library ieee;
use ieee.numeric_bit.all;

entity bcd_adder is
	
	port (x,y : in unsigned (7 downto 0);
	    	z: out unsigned(11 downto 0));
			
end bcd_adder;	

architecture bcdadd of bcd_adder is

alias Xdig1: unsigned(3 downto 0) is x(7 downto 4);
alias Xdig0: unsigned(3 downto 0) is x(3 downto 0);
alias Ydig1: unsigned(3 downto 0) is y(7 downto 4);
alias Ydig0: unsigned(3 downto 0) is y(3 downto 0);	
alias Zdig2: unsigned(3 downto 0) is z(11 downto 8);
alias Zdig1: unsigned(3 downto 0) is z(7 downto 4);
alias Zdig0: unsigned(3 downto 0) is z(3 downto 0);

signal s0, s1: unsigned (4 downto 0);
signal c: bit;

begin 
s0 <= '0' & Xdig0 + Ydig0; --overloaded +

Zdig0 <= s0(3 downto 0) + 6 when s0 > 9 
	else  s0(3 downto 0); --add 6 if needed

c <= '1' when s0 > 9
	else '0';

s1 <= '0' & Xdig1 + Ydig1 + unsigned'(0=>c); --type conversion done C before adding

Zdig1 <= s1(3 downto 0) + 6 when s1 > 9 
	else s1(3 downto 0);
 
Zdig2 <= "0001" when s1 > 9 else "0000";

end bcdadd;

Testbench

• Código
• Resultado (print)

Simulações

Nº Bits	ALMs	Delay	Potência (mW)
x	x	x	x
x	x	x	x
x	x	x	x
x	x	x	x