Circuito Somador - John

Código VHDL

--Book: John/199
--32 bits
library ieee;
use ieee.numeric_bit.all;

entity adder is

	port(
		a,b: in unsigned (31 downto 0);
		ci: in bit;
		s: out unsigned (31 downto 0);
		co: out bit);
end entity;

architecture adder of adder is
	signal sum33 : unsigned (32 downto 0);

begin 
	sum33 <= '0' & a + b + unsigned'(0 => ci);
	s <= sum33(31 downto 0);
	co <= sum33(32);
end architecture;

Testbench

• Código
• Resultado (print)

Simulações

Nº Bits	ALMs	Delay	Potência (mW)
x	x	x	x
x	x	x	x
x	x	x	x
x	x	x	x