Testebench multiplicador
Ir para navegação
Ir para pesquisar
-- Testbench created online at:
-- www.doulos.com/knowhow/perl/testbench_creation/
-- Copyright Doulos Ltd
-- SD, 03 November 2002
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity DUT_tb_mult is
GENERIC ( n_DUT : INTEGER := 64;
bits_DUT : INTEGER := 6
);
end entity;
architecture bench of DUT_tb_mult is
component DUT_mult is
GENERIC (n_DUT : INTEGER := 64; -- Dados seriais transmitidos
bits_DUT : INTEGER := 6 -- Bits do contador interno log2(n)
);
PORT
(
inclk0 : IN STD_LOGIC;
din0 : IN STD_LOGIC;
din1 : IN STD_LOGIC;
cin : IN STD_LOGIC;
doutS : OUT STD_LOGIC;
prod_DUT: OUT STD_LOGIC_VECTOR(2*n_DUT-1 DOWNTO 0)
);
END component;
signal cin : STD_LOGIC := '0';
signal din0 : STD_LOGIC := '0';
signal din1 : STD_LOGIC := '0';
signal inclk0 : STD_LOGIC := '0';
signal doutS: STD_LOGIC := '0';
constant max: NATURAL := 65536;--4000;
signal prod_int: INTEGER range 0 to 2*max;
signal erro: STD_LOGIC;
signal a_old, b_old : STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
signal prod : STD_LOGIC_VECTOR(2*n_DUT-1 DOWNTO 0);
signal a,b: std_logic_vector(n_DUT-1 downto 0);
constant clock_half_period: time := 10 ns;
constant tp: time := 10ns;
constant clock_period: time := clock_half_period*2;
constant ab_rate: time := clock_period * n_DUT;
constant din_rate: time := clock_half_period*2*bits_DUT;
constant op_time: time := (n_DUT*ab_rate);
signal stop_the_clock: boolean;
begin
uut: DUT_mult
generic map (bits_DUT => bits_DUT, n_DUT => n_DUT)
port map ( inclk0 => inclk0,
din0 => din0,
din1 => din1,
cin => cin,
doutS => doutS,
prod_DUT => prod);
inclk0 <= not inclk0 after clock_half_period;
--
--din0_int <= 1 when din0='1' else 0;
--din1_int <= 1 when din1='1' else 0;
--doutS_int <= 1 when doutS='1' else 0;
stimulus_vect: process
variable a,b: std_logic_vector(n_DUT-1 downto 0);
begin
--for i in 255 to (2**n-1) loop
for i in 0 to max loop
a := std_logic_vector(to_unsigned(2*i,n_DUT));
b := std_logic_vector(to_unsigned(i,n_DUT)); --21854 - 555H
for i in 0 to n_DUT-1 loop
din0 <= a(i);
din1 <= b(i);
wait for clock_period;
end loop;
-- wait for ab_rate;
a_old <= a;
b_old <= b;
end loop;
end process;
prod_int <= to_integer(unsigned(prod));
test: process
begin
wait for tp;
for i in 0 to max loop
wait for clock_period*n_DUT;
if (prod_int = to_integer(unsigned(a_old)) * to_integer(unsigned(b_old))) then erro <= '0'; else erro <= '1'; end if;
assert (prod_int = to_integer(unsigned(a_old)) * to_integer(unsigned(b_old)))
report "ERRO na operacao de multiplicacao quando" & "(a = " & integer'image(to_integer(unsigned(a_old))) & ", b = " & integer'image(to_integer(unsigned(b_old))) & ", prod = " & integer'image(prod_int) & ")."
severity FAILURE;
end loop;
end process;
end;