Circuito Somador e Subtrator - Chu

Código VHDL

--Book: Chu/172
--8 bits
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity addsub is 
	port( a,b: in std_logic_vector (7 downto 0);
			ctrl: in std_logic;
			r: out std_logic_vector(7 downto 0));
			
end entity;

architecture direct_Arch of addsub is
	signal src0, src1, sum: signed (7 downto 0);

begin
	src0 <= signed(a);
	src1 <= signed(b);
	sum  <= src0 + src1 when ctrl='0' else	
			  src0 - src1;
	r<= std_logic_vector(sum);
end architecture;

Testbench

• Código
• Resultado (print)

Simulações

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