Testebench somador

-- Testbench created online at:
--   www.doulos.com/knowhow/perl/testbench_creation/
-- Copyright Doulos Ltd
-- SD, 03 November 2002

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;


entity DUT_tb_adder is
GENERIC (n_DUT : INTEGER := 16;	-- Dados seriais transmitidos
			bits_DUT : INTEGER := 4; -- Bits do contador interno log2(n)
			k_DUT : integer := 16;
			m_DUT : integer := 1
			);
end entity;



architecture bench of DUT_tb_adder is

component DUT_adder is

GENERIC (n_DUT : INTEGER := 16;	-- Dados seriais transmitidos
			bits_DUT : INTEGER := 4; -- Bits do contador interno log2(n)
			k_DUT : integer := 16;
			m_DUT : integer := 1
			);
	PORT
	(
		inclk0 :  IN  STD_LOGIC;
		din0 :  IN  STD_LOGIC;
		din1 :  IN  STD_LOGIC;
		cin : IN  STD_LOGIC;
		doutS :  OUT  STD_LOGIC;
 	   sum_DUT : OUT STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0) 
		-- PARA DEPUARAAO  --RETIRAR PARA MEDIR DESEMPENHO
	);
END component;

		
		signal cin : std_logic := '0';
		signal din0 : STD_LOGIC := '0';
		signal din1 : STD_LOGIC := '0';
		signal inclk0 : STD_LOGIC := '0';
		signal doutS:  STD_LOGIC := '0';
		
--		signal din0_int : INTEGER range 0 to 1;
--		signal din1_int : INTEGER range 0 to 1;
--      constant max: NATURAL := 4000;
--	   signal sum_int:  INTEGER range 0 to 2**(n_DUT/2)-1 := 0;
		constant max: NATURAL := 2000; --65536; --2000; --
	   signal sum_int:  INTEGER range 0 to 65536; --10*max;
	   signal erro: STD_LOGIC;
		signal a_old, b_old , sum: STD_LOGIC_VECTOR(n_DUT-1 DOWNTO 0);
		signal a,b: std_logic_vector(n_DUT-1 downto 0);
		
		constant clock_half_period: time := 10 ns; 
		constant tp: time := 10ns;
		constant clock_period: time :=  clock_half_period*2;
		constant ab_rate: time := clock_period * n_DUT;
		constant din_rate: time := clock_half_period*2*bits_DUT; 
		constant op_time: time := (n_DUT*ab_rate);				
		signal stop_the_clock: boolean;
	
begin

  uut: DUT_adder
				generic map (bits_DUT =>  bits_DUT, n_DUT => n_DUT) 
				port map ( inclk0       => inclk0,
								cin 			=> cin,
                        din0        => din0,
								din1        => din1,
								doutS       => doutS,
								sum_DUT => sum);

 
inclk0 <= not inclk0 after clock_half_period;
 
  stimulus_vect: process
	variable a,b: std_logic_vector(n_DUT-1 downto 0);
  begin
		for i in 0 to max loop
 			a := std_logic_vector(to_unsigned(i,n_DUT)); 
 			b := std_logic_vector(to_unsigned(max-i,n_DUT)); 
		    for i in 0 to n_DUT-1 loop
			 din0 <= a(i);
			 din1 <= b(i);
			 wait for clock_period;	
	        end loop;
		--	wait for ab_rate; 
			a_old <= a;
			b_old <= b;
	
		end loop;	
  end process;

sum_int <= to_integer(unsigned(sum));
--sum_int <= to_integer(unsigned(sum)) when a_old(10) = '0' else 0;

test: process
	  begin
           wait for tp;
           		for i in 0 to max loop
        	    wait for clock_period*n_DUT;
           	    if  (sum_int = to_integer(unsigned(a_old)) + to_integer(unsigned(b_old))) then erro <= '0'; else erro <= '1'; end if;
    
        		assert (sum_int = to_integer(unsigned(a_old)) + to_integer(unsigned(b_old)))
        			report "ERRO na operacao de soma quando" & "(a = " & integer'image(to_integer(unsigned(a_old))) & ", b = " & integer'image(to_integer(unsigned(b_old))) & ", sum = " & integer'image(sum_int) & ")."
        			severity FAILURE;
    		end loop;
	end process;

 end;