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Figura 1 - Níveis e chaveamento digital
Fonte: Selecting the Right Level-Translation Solution - TI.
Quadro 1 - I/O Standards Support for FPGA I/O in Intel® Arria® 10 Devices
FONTE: Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook
Linha 2: | Linha 2: | ||
{{fig|1|Níveis e chaveamento digital | LogicSwitching.png| 1200 px | [https://www.ti.com/lit/an/scea035a/scea035a.pdf Selecting the Right Level-Translation Solution - TI]}} | {{fig|1|Níveis e chaveamento digital | LogicSwitching.png| 1200 px | [https://www.ti.com/lit/an/scea035a/scea035a.pdf Selecting the Right Level-Translation Solution - TI]}} | ||
+ | <center> Quadro 1 - I/O Standards Support for FPGA I/O in Intel® Arria® 10 Devices </center> | ||
+ | {| class="wikitable" style="text-align:center;" | ||
+ | |- style="font-weight:bold; background-color:#c0c0c0; color:#333;" | ||
+ | ! rowspan="2" | I/O Standard | ||
+ | ! rowspan="2" | Device Variant Support | ||
+ | ! colspan="2" | I/O Buffer Type Support | ||
+ | ! rowspan="2" | Application | ||
+ | ! rowspan="2" | Standard Support | ||
+ | |- style="font-weight:bold; color:#333;" | ||
+ | | style="background-color:#c0c0c0;" | LVDS I/O | ||
+ | | style="background-color:#c0c0c0; text-align:left;" | 3V I/O | ||
+ | |- | ||
+ | | 3.0 V LVTTL/3.0 V LVCMOS | ||
+ | | Devices with 3 V I/O banks only. | ||
+ | | No | ||
+ | | style="text-align:left;" | Yes | ||
+ | | General purpose | ||
+ | | JESD8-B | ||
+ | |- | ||
+ | | 2.5 V LVCMOS | ||
+ | | Devices with 3 V I/O banks only. | ||
+ | | No | ||
+ | | style="text-align:left;" | Yes | ||
+ | | General purpose | ||
+ | | JESD8-5 | ||
+ | |- | ||
+ | | 1.8 V LVCMOS | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | General purpose | ||
+ | | JESD8-7 | ||
+ | |- | ||
+ | | 1.5 V LVCMOS | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | General purpose | ||
+ | | JESD8-11 | ||
+ | |- | ||
+ | | 1.2 V LVCMOS | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | General purpose | ||
+ | | JESD8-12 | ||
+ | |- | ||
+ | | SSTL-18 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR2 | ||
+ | | JESD8-15 | ||
+ | |- | ||
+ | | SSTL-15 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR3 | ||
+ | | — | ||
+ | |- | ||
+ | | SSTL-15 | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR3 | ||
+ | | JESD79-3D | ||
+ | |- | ||
+ | | SSTL-135, SSTL-135 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR3L | ||
+ | | — | ||
+ | |- | ||
+ | | SSTL-125, SSTL-125 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR3U | ||
+ | | — | ||
+ | |- | ||
+ | | SSTL-12, SSTL-12 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | No | ||
+ | | RLDRAM 3 | ||
+ | | — | ||
+ | |- | ||
+ | | POD12 | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | No | ||
+ | | DDR4 | ||
+ | | JESD8-24 | ||
+ | |- | ||
+ | | 1.8 V HSTL Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR II+, QDR II+, and RLDRAM 2 | ||
+ | | JESD8-6 | ||
+ | |- | ||
+ | | 1.5 V HSTL Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR II+, QDR II+, QDR II, and RLDRAM 2 | ||
+ | | JESD8-6 | ||
+ | |- | ||
+ | | 1.2 V HSTL Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | General purpose | ||
+ | | JESD8-16A | ||
+ | |- | ||
+ | | HSUL-12 | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | LPDDR2 | ||
+ | | — | ||
+ | |- | ||
+ | | Differential SSTL-18 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR2 | ||
+ | | JESD8-15 | ||
+ | |- | ||
+ | | Differential SSTL-15 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR3 | ||
+ | | — | ||
+ | |- | ||
+ | | Differential SSTL-15 | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR3 | ||
+ | | JESD79-3D | ||
+ | |- | ||
+ | | Differential SSTL-135, SSTL-135 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR3L | ||
+ | | — | ||
+ | |- | ||
+ | | Differential SSTL-125, SSTL-125 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR3U | ||
+ | | — | ||
+ | |- | ||
+ | | Differential SSTL-12, SSTL-12 Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | No | ||
+ | | RLDRAM 3 | ||
+ | | — | ||
+ | |- | ||
+ | | Differential POD12 | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | No | ||
+ | | DDR4 | ||
+ | | JESD8-24 | ||
+ | |- | ||
+ | | Differential 1.8 V HSTL Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR II+, QDR II+, and RLDRAM 2 | ||
+ | | JESD8-6 | ||
+ | |- | ||
+ | | Differential 1.5 V HSTL Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | DDR II+, QDR II+, QDR II, and RLDRAM 2 | ||
+ | | JESD8-6 | ||
+ | |- | ||
+ | | Differential 1.2 V HSTL Class I and Class II | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | General purpose | ||
+ | | JESD8-16A | ||
+ | |- | ||
+ | | Differential HSUL-12 | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | Yes | ||
+ | | LPDDR2 | ||
+ | | — | ||
+ | |- | ||
+ | | LVDS | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | No | ||
+ | | SGMII, SFI, and SPI | ||
+ | | ANSI/TIA/EIA-644 | ||
+ | |- | ||
+ | | Mini-LVDS | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | No | ||
+ | | SGMII, SFI, and SPI | ||
+ | | — | ||
+ | |- | ||
+ | | RSDS | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | No | ||
+ | | SGMII, SFI, and SPI | ||
+ | | — | ||
+ | |- | ||
+ | | LVPECL | ||
+ | | All | ||
+ | | Yes | ||
+ | | style="text-align:left;" | No | ||
+ | | SGMII, SFI, and SPI | ||
+ | | — | ||
+ | |} | ||
+ | <center> FONTE: [https://www.intel.com/content/www/us/en/docs/programmable/683461/current/i-o-standards-support-for-fpga-i-o-in.html Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook] </center> | ||
+ | |||
+ | <!-- | ||
:[[Arquivo:TI_CMOS_Voltage_vs_Speed.png]] | :[[Arquivo:TI_CMOS_Voltage_vs_Speed.png]] | ||
FONTE: [http://www.elec.canterbury.ac.nz/intranet/dsl/p90-links/doc-include/logic/ti-migration-guide.pdf LOGIC MIGRATION GUIDE] - Texas Instruments Incorporated | FONTE: [http://www.elec.canterbury.ac.nz/intranet/dsl/p90-links/doc-include/logic/ti-migration-guide.pdf LOGIC MIGRATION GUIDE] - Texas Instruments Incorporated | ||
Linha 9: | Linha 241: | ||
*[http://digsys.upc.es/csd/units/Elect/TI_Digital_Logic_Families.pdf Digital Logic Family Selection Matrix (Sorted by Speed)] | *[http://digsys.upc.es/csd/units/Elect/TI_Digital_Logic_Families.pdf Digital Logic Family Selection Matrix (Sorted by Speed)] | ||
+ | --> | ||
==O que é a margem de ruído?== | ==O que é a margem de ruído?== |
Edição das 18h49min de 3 de agosto de 2023
Quais são as famílias lógicas dos circuitos digitais?
Figura 1 - Níveis e chaveamento digital
I/O Standard | Device Variant Support | I/O Buffer Type Support | Application | Standard Support | |
---|---|---|---|---|---|
LVDS I/O | 3V I/O | ||||
3.0 V LVTTL/3.0 V LVCMOS | Devices with 3 V I/O banks only. | No | Yes | General purpose | JESD8-B |
2.5 V LVCMOS | Devices with 3 V I/O banks only. | No | Yes | General purpose | JESD8-5 |
1.8 V LVCMOS | All | Yes | Yes | General purpose | JESD8-7 |
1.5 V LVCMOS | All | Yes | Yes | General purpose | JESD8-11 |
1.2 V LVCMOS | All | Yes | Yes | General purpose | JESD8-12 |
SSTL-18 Class I and Class II | All | Yes | Yes | DDR2 | JESD8-15 |
SSTL-15 Class I and Class II | All | Yes | Yes | DDR3 | — |
SSTL-15 | All | Yes | Yes | DDR3 | JESD79-3D |
SSTL-135, SSTL-135 Class I and Class II | All | Yes | Yes | DDR3L | — |
SSTL-125, SSTL-125 Class I and Class II | All | Yes | Yes | DDR3U | — |
SSTL-12, SSTL-12 Class I and Class II | All | Yes | No | RLDRAM 3 | — |
POD12 | All | Yes | No | DDR4 | JESD8-24 |
1.8 V HSTL Class I and Class II | All | Yes | Yes | DDR II+, QDR II+, and RLDRAM 2 | JESD8-6 |
1.5 V HSTL Class I and Class II | All | Yes | Yes | DDR II+, QDR II+, QDR II, and RLDRAM 2 | JESD8-6 |
1.2 V HSTL Class I and Class II | All | Yes | Yes | General purpose | JESD8-16A |
HSUL-12 | All | Yes | Yes | LPDDR2 | — |
Differential SSTL-18 Class I and Class II | All | Yes | Yes | DDR2 | JESD8-15 |
Differential SSTL-15 Class I and Class II | All | Yes | Yes | DDR3 | — |
Differential SSTL-15 | All | Yes | Yes | DDR3 | JESD79-3D |
Differential SSTL-135, SSTL-135 Class I and Class II | All | Yes | Yes | DDR3L | — |
Differential SSTL-125, SSTL-125 Class I and Class II | All | Yes | Yes | DDR3U | — |
Differential SSTL-12, SSTL-12 Class I and Class II | All | Yes | No | RLDRAM 3 | — |
Differential POD12 | All | Yes | No | DDR4 | JESD8-24 |
Differential 1.8 V HSTL Class I and Class II | All | Yes | Yes | DDR II+, QDR II+, and RLDRAM 2 | JESD8-6 |
Differential 1.5 V HSTL Class I and Class II | All | Yes | Yes | DDR II+, QDR II+, QDR II, and RLDRAM 2 | JESD8-6 |
Differential 1.2 V HSTL Class I and Class II | All | Yes | Yes | General purpose | JESD8-16A |
Differential HSUL-12 | All | Yes | Yes | LPDDR2 | — |
LVDS | All | Yes | No | SGMII, SFI, and SPI | ANSI/TIA/EIA-644 |
Mini-LVDS | All | Yes | No | SGMII, SFI, and SPI | — |
RSDS | All | Yes | No | SGMII, SFI, and SPI | — |
LVPECL | All | Yes | No | SGMII, SFI, and SPI | — |
O que é a margem de ruído?
FONTE: How to Select Little Logic - Texas Instruments Incorporated
Obsolescência das famílias lógicas
FONTE: [1]
Encapsulamento de circuitos lógicos
FONTE: LOGIC MIGRATION GUIDE - Texas Instruments (TI)