Níveis lógicos

Quais são as famílias lógicas dos circuitos digitais?

Figura 1 - Níveis e chaveamento digital Fonte: Selecting the Right Level-Translation Solution - TI.
Quadro 1 - I/O Standards Support for FPGA I/O in Intel® Arria® 10 Devices

I/O Standard	Device Variant Support	I/O Buffer Type Support		Application	Standard Support
		LVDS I/O	3V I/O
3.0 V LVTTL/3.0 V LVCMOS	Devices with 3 V I/O banks only.	No	Yes	General purpose	JESD8-B
2.5 V LVCMOS	Devices with 3 V I/O banks only.	No	Yes	General purpose	JESD8-5
1.8 V LVCMOS	All	Yes	Yes	General purpose	JESD8-7
1.5 V LVCMOS	All	Yes	Yes	General purpose	JESD8-11
1.2 V LVCMOS	All	Yes	Yes	General purpose	JESD8-12
SSTL-18 Class I and Class II	All	Yes	Yes	DDR2	JESD8-15
SSTL-15 Class I and Class II	All	Yes	Yes	DDR3	—
SSTL-15	All	Yes	Yes	DDR3	JESD79-3D
SSTL-135, SSTL-135 Class I and Class II	All	Yes	Yes	DDR3L	—
SSTL-125, SSTL-125 Class I and Class II	All	Yes	Yes	DDR3U	—
SSTL-12, SSTL-12 Class I and Class II	All	Yes	No	RLDRAM 3	—
POD12	All	Yes	No	DDR4	JESD8-24
1.8 V HSTL Class I and Class II	All	Yes	Yes	DDR II+, QDR II+, and RLDRAM 2	JESD8-6
1.5 V HSTL Class I and Class II	All	Yes	Yes	DDR II+, QDR II+, QDR II, and RLDRAM 2	JESD8-6
1.2 V HSTL Class I and Class II	All	Yes	Yes	General purpose	JESD8-16A
HSUL-12	All	Yes	Yes	LPDDR2	—
Differential SSTL-18 Class I and Class II	All	Yes	Yes	DDR2	JESD8-15
Differential SSTL-15 Class I and Class II	All	Yes	Yes	DDR3	—
Differential SSTL-15	All	Yes	Yes	DDR3	JESD79-3D
Differential SSTL-135, SSTL-135 Class I and Class II	All	Yes	Yes	DDR3L	—
Differential SSTL-125, SSTL-125 Class I and Class II	All	Yes	Yes	DDR3U	—
Differential SSTL-12, SSTL-12 Class I and Class II	All	Yes	No	RLDRAM 3	—
Differential POD12	All	Yes	No	DDR4	JESD8-24
Differential 1.8 V HSTL Class I and Class II	All	Yes	Yes	DDR II+, QDR II+, and RLDRAM 2	JESD8-6
Differential 1.5 V HSTL Class I and Class II	All	Yes	Yes	DDR II+, QDR II+, QDR II, and RLDRAM 2	JESD8-6
Differential 1.2 V HSTL Class I and Class II	All	Yes	Yes	General purpose	JESD8-16A
Differential HSUL-12	All	Yes	Yes	LPDDR2	—
LVDS	All	Yes	No	SGMII, SFI, and SPI	ANSI/TIA/EIA-644
Mini-LVDS	All	Yes	No	SGMII, SFI, and SPI	—
RSDS	All	Yes	No	SGMII, SFI, and SPI	—
LVPECL	All	Yes	No	SGMII, SFI, and SPI	—

FONTE: Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

Ler mais em

• Selectable I/O Standards in Stratix & Stratix GX Devices
• Supported I/O Standards Microchip

O que fazer quando se trabalha com diferentes tensões lógicas?

• Uma das possíveis soluções é usar circuitos apropriados para translação das tensões. Um excelente guia para isso é o Voltage translators & level shifters da Texas Instruments. Alguns exemplos são mostrados no Application Report Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards.
• Um exemplo é o Application Report Voltage-Level Translation With the LSF Family. Sua aplicação para tensão de entrada de 1.8V e saída de 3.3V é ilustrada na simulação no FALSTAD.

O que é a margem de ruído?

FONTE: How to Select Little Logic - Texas Instruments Incorporated

Obsolescência das famílias lógicas

FONTE: [1]

Encapsulamento de circuitos lógicos

FONTE: LOGIC MIGRATION GUIDE - Texas Instruments (TI)

LINKS

• [2]
• Power consumption