Mudanças entre as edições de "Cronograma de atividades (STE-EngTel)"

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(Criou página com '{{collapse top| bg=lightgreen | expandir=true |Semestre 2015-2 - Prof. Arliones Hoeller}} {{Cronograma-top}} {{Cl|1 |2/10 | 2 | Introduction to Embedded Systems: History Overview...')
 
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{{Cl|1 |2/10 | 2 | Introduction to Embedded Systems: History Overview and Fundamental Concepts. | Lab. Redes I}}
 
{{Cl|1 |2/10 | 2 | Introduction to Embedded Systems: History Overview and Fundamental Concepts. | Lab. Redes I}}
 
{{Cl|2 |6/10 | 2 | Embedded Systems Development: Design Principles. | Lab. Redes I}}
 
{{Cl|2 |6/10 | 2 | Embedded Systems Development: Design Principles. | Lab. Redes I}}
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{{Cl|3 |9/10 | 2 | Embedded Systems Development: Real-Time Constraints. | Lab. Redes I}}
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{{Cl|3 |9/10 | 2,4 | Embedded Systems Development: Real-Time Constraints. | Lab. Redes I}}
 
{{Cl|4 |13/10 | 2 | Embedded Systems Development: Implementation Techniques. | Lab. Redes I}}
 
{{Cl|4 |13/10 | 2 | Embedded Systems Development: Implementation Techniques. | Lab. Redes I}}
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{{Cl|5 |16/10 | 2 | Embedded Systems Development: Testing, Emulation and Debugging Techniques. | Lab. Redes I}}
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{{Cl|5 |16/10 | 2,4 | Embedded Systems Development: Testing, Emulation and Debugging Techniques. | Lab. Redes I}}
 
{{Cl|6 |20/10 | 2 | I/O Basics: I/O Ports. | Lab. Redes I}}
 
{{Cl|6 |20/10 | 2 | I/O Basics: I/O Ports. | Lab. Redes I}}
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{{Cl|7 |23/10 | 2 | I/O Basics: Interrupt Handling. | Lab. Redes I}}
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{{Cl|7 |23/10 | 2,4 | I/O Basics: Interrupt Handling. | Lab. Redes I}}
 
{{Cl|8 |27/10 | 2 | I/O Basics: Programmed I/O and DMA. | Lab. Redes I}}
 
{{Cl|8 |27/10 | 2 | I/O Basics: Programmed I/O and DMA. | Lab. Redes I}}
 
{{Cl|9 |3/11 | 2 | Timers and Counters. | Lab. Redes I}}
 
{{Cl|9 |3/11 | 2 | Timers and Counters. | Lab. Redes I}}
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{{Cl|10 |6/11 | 2 | Watchdog and Real-Time Clock. | Lab. Redes I}}
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{{Cl|10 |6/11 | 2,4 | Watchdog and Real-Time Clock. | Lab. Redes I}}
 
{{Cl|11 |10/11 | 2 | Interfacing to the Analog World: ADC and Sensors. | Lab. Redes I}}
 
{{Cl|11 |10/11 | 2 | Interfacing to the Analog World: ADC and Sensors. | Lab. Redes I}}
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{{Cl|12 |13/11 | 2 | Interfacing to the Analog World: DAC and Actuators. | Lab. Redes I}}
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{{Cl|12 |13/11 | 2,4 | Interfacing to the Analog World: DAC and Actuators. | Lab. Redes I}}
 
{{Cl|13 |17/11 | 2 | Introduction to Real-Time Systems: Fundamentals and Periodic Scheduling. | Lab. Redes I}}
 
{{Cl|13 |17/11 | 2 | Introduction to Real-Time Systems: Fundamentals and Periodic Scheduling. | Lab. Redes I}}
 
{{Cl|14 |20/11 | 2 | Introduction to Real-Time Systems: Aperiodic Scheduling and Priority Inversion. | Lab. Redes I}}
 
{{Cl|14 |20/11 | 2 | Introduction to Real-Time Systems: Aperiodic Scheduling and Priority Inversion. | Lab. Redes I}}
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{{Cl|21 |15/12 | 2 | Final Project: Specification and Analysis | Lab Redes I}}
 
{{Cl|21 |15/12 | 2 | Final Project: Specification and Analysis | Lab Redes I}}
 
{{Cl|22 |18/12 | 2 | Final Project: Specification and Analysis – Checkpoint | Lab Redes I}}
 
{{Cl|22 |18/12 | 2 | Final Project: Specification and Analysis – Checkpoint | Lab Redes I}}
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{{Cl|23 |22/12 | 2 | Final Project: Specification and Analysis – Presentation | Lab Redes I}}
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{{Cl|24 |2/2 | 2 | Final Project: Specification and Analysis – Presentation | Lab Redes I}}
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{{Cl|24 |2/2 | 2 | Final Project: Implementation | Lab Redes I}}
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{{Cl|25 |5/2 | 2 | Final Project: Implementation | Lab Redes I}}
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{{Cl|25 |5/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}}
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{{Cl|26 |12/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}}
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{{Cl|26 |12/2 | 2 | Final Project: Implementation | Lab Redes I}}
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{{Cl|27 |16/2 | 2 | Final Project: Implementation | Lab Redes I}}
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{{Cl|27 |16/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}}
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{{Cl|28 |19/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}}
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{{Cl|28 |19/2 | 2 | Final Project: Implementation | Lab Redes I}}
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{{Cl|29 |23/2 | 2 | Final Project: Implementation | Lab Redes I}}
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{{Cl|29 |23/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}}
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{{Cl|30 |26/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}}
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{{Cl|30 |26/2 | 2 | Final Project: Implementation | Lab Redes I}}
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{{Cl|31 |1/3 | 2 | Final Project: Implementation | Lab Redes I}}
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{{Cl|31 |1/3 | 2 | Final Project: Implementation – Presentation | Lab Redes I}}
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{{Cl|32 |4/3 | 2 | Final Project: Implementation – Presentation | Lab Redes I}}
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{{Cl|32 |4/3 | 2 | Final Project: Integration | Lab Redes I}}
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{{Cl|33 |8/3 | 2 | Final Project: Integration | Lab Redes I}}
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{{Cl|33 |8/3 | 2 | Final Project: Integration – Checkpoint | Lab Redes I}}
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{{Cl|34 |11/3 | 2 | Final Project: Integration – Checkpoint | Lab Redes I}}
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{{Cl|34 |11/3 | 2 | Final Project: Integration | Lab Redes I}}
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{{Cl|35 |15/3 | 2 | Final Project: Integration | Lab Redes I}}
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{{Cl|35 |15/3 | 2 | Final Project: Integration – Presentation | Lab Redes I}}
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{{Cl|36 |18/3 | 2 | Final Project: Integration – Presentation | Lab Redes I}}
 
 
{{cronograma-botton |72}}
 
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Edição das 15h17min de 26 de outubro de 2015

Semestre 2015-2 - Prof. Arliones Hoeller
Aula Data Horas Conteúdo Recursos
1 2/10 2 Introduction to Embedded Systems: History Overview and Fundamental Concepts. Lab. Redes I
2 6/10 2 Embedded Systems Development: Design Principles. Lab. Redes I
3 9/10 2,4 Embedded Systems Development: Real-Time Constraints. Lab. Redes I
4 13/10 2 Embedded Systems Development: Implementation Techniques. Lab. Redes I
5 16/10 2,4 Embedded Systems Development: Testing, Emulation and Debugging Techniques. Lab. Redes I
6 20/10 2 I/O Basics: I/O Ports. Lab. Redes I
7 23/10 2,4 I/O Basics: Interrupt Handling. Lab. Redes I
8 27/10 2 I/O Basics: Programmed I/O and DMA. Lab. Redes I
9 3/11 2 Timers and Counters. Lab. Redes I
10 6/11 2,4 Watchdog and Real-Time Clock. Lab. Redes I
11 10/11 2 Interfacing to the Analog World: ADC and Sensors. Lab. Redes I
12 13/11 2,4 Interfacing to the Analog World: DAC and Actuators. Lab. Redes I
13 17/11 2 Introduction to Real-Time Systems: Fundamentals and Periodic Scheduling. Lab. Redes I
14 20/11 2 Introduction to Real-Time Systems: Aperiodic Scheduling and Priority Inversion. Lab. Redes I
15 24/11 2 Embedded Real-Time Operating Systems Lab. Redes I
16 27/11 2 Networking: Field Buses and CAN. Lab. Redes I
17 1/12 2 Networking: Wireless Control Networks and IEEE 802.15.4. Lab. Redes I
18 4/12 2 Networking: Ethernet. Lab. Redes I
19 8/12 2 Final Project: System Vision Document Lab. Redes I
20 11/12 2 Final Project: System Vision Document – Presentation Lab. Redes I
21 15/12 2 Final Project: Specification and Analysis Lab Redes I
22 18/12 2 Final Project: Specification and Analysis – Checkpoint Lab Redes I
23 22/12 2 Final Project: Specification and Analysis – Presentation Lab Redes I
24 2/2 2 Final Project: Implementation Lab Redes I
25 5/2 2 Final Project: Implementation – Checkpoint Lab Redes I
26 12/2 2 Final Project: Implementation Lab Redes I
27 16/2 2 Final Project: Implementation – Checkpoint Lab Redes I
28 19/2 2 Final Project: Implementation Lab Redes I
29 23/2 2 Final Project: Implementation – Checkpoint Lab Redes I
30 26/2 2 Final Project: Implementation Lab Redes I
31 1/3 2 Final Project: Implementation – Presentation Lab Redes I
32 4/3 2 Final Project: Integration Lab Redes I
33 8/3 2 Final Project: Integration – Checkpoint Lab Redes I
34 11/3 2 Final Project: Integration Lab Redes I
35 15/3 2 Final Project: Integration – Presentation Lab Redes I
TOTAL 72
Disponível em “https://wiki.sj.ifsc.edu.br/index.php?title=Cronograma_de_atividades_(STE-EngTel)&oldid=95515”