Configuração e uso do Signal Tap

O software Quartus® II possui uma ferramenta de depuração a nível de sistema chamado SignalTap II que pode capturar e mostrar os sinais em qualquer FPGA em tempo real.

• Para configurar o SignalTap II, consulte o tutorial da ALTERA SIGNAL TAP II WITH VHDL DESIGNS.
• Mais informações podem ser encontradas em Design Debugging Using the SignalTap II Logic Analyzer

Resumo das dicas para uso

• 1. Open the SignalTap II window by selecting [File > New], which gives the window shown in Figure 3. Choose SignalTap II Logic Analyzer File and click [OK].
• 2. Save the file under the name "filename.stp". Click OK. For the dialog "Do you want to enable SignalTap II file "filename.stp" for the current project?" click Yes. The file "filename.stp" is now the SignalTap file associated with the project.
• 3. We now need to add the nodes in the project that we wish to probe. In the Setup tab of the SignalTap II window, double-click in the area labeled Double-click to add nodes, bringing up the Node Finder window. Click on [$\downarrow$] to show more search options. For the Filter field, select [SignalTap II:pre-synthesis]. Click [List]. This will now display all the nodes that can be probed in the project. Select the nodes you want to probe, and then click the button [>>] to add them to be probed. Then click [OK].
• 4. Before the SignalTap analyzer can work, we need to specify what clock is going to run the SignalTap module that will be instantiated within our design. To do this, in the Clock box of the Signal Configuration pane of the SignalTap window, click [...], which will again bring up the Node Finder window. Select List to display all the nodes that can be added as the clock, and then double-click 'your_clock'. Click [OK].