Carry Select

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--Book: GUIDE/159
-- Carry select adder

architecture adder_carry_select OF adder is

 COMPONENT carry_select IS
    GENERIC(k: NATURAL);
  PORT(
    x, y: IN STD_LOGIC_VECTOR(k-1 DOWNTO 0);
    cin: IN STD_LOGIC;
    z: OUT STD_LOGIC_VECTOR(k-1 DOWNTO 0);
    c_out: OUT STD_LOGIC
  );
  END COMPONENT;
  SIGNAL carries: STD_LOGIC_VECTOR(m DOWNTO 0);
  signal c_out : std_logic;
BEGIN
  carries(0) <= cin;
  iteration: FOR i IN 0 TO m-1 GENERATE
    main_component:carry_select 
	 GENERIC MAP(k => k)
    PORT MAP(x => a(k*i+k-1 DOWNTO k*i),
	 y => b(k*i+k-1 DOWNTO k*i), 
	 cin => carries(i),
    z => sum(k*i+k-1 DOWNTO k*i),
	 c_out => carries(i+1));
  END GENERATE;
  c_out <= carries(m);
END architecture;