Carry Lookahead 4 bits

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--Book: Eletronica digital moderna e VHDL/490
-- Carry lookahead com 4 bits

architecture adder_carry_lookahead_4 of adder is

	signal carry: std_logic_vector(n/4 downto 0); 
	
	component carry_lookahead_adder_4 is
			port( a,b : in std_logic_vector(3 downto 0);
			cin: in std_logic;
			cout: out std_logic;
			sum: out std_logic_vector(3 downto 0));
	end component;
	
begin
	carry(0) <= cin;
	gen_adder: for i in 1 to n/4 generate
		adder: carry_lookahead_adder_4 
			port map(
				a => a(4*i-1 downto 4*i-4),
				b => b(4*i-1 downto 4*i-4),
				cin => carry(i-1),
				sum => sum(4*i-1 downto 4*i-4),
				cout => carry(i)
			);
		end generate;
		
end architecture; 

-------------------------------------------------
--Book: Pedroni/490
--4 bits carry-lookahead
--Uso do component
library ieee;
use ieee.std_logic_1164.all;

entity carry_lookahead_adder_4 is
	port( a,b : in std_logic_vector(3 downto 0);
			cin: in std_logic;
			cout: out std_logic;
			sum: out std_logic_vector(3 downto 0));
end entity;

architecture structure of carry_lookahead_adder_4 is
		signal g,p,c : std_logic_vector(3 downto 0);
	
	begin	
	---computation of g and p;
		g <= a and b; 
		p <= a xor b;
		
	---computation of carry;
		c(0) <= cin;
		
		c(1) <= g(0) or 
				 (p(0) and cin);
		
		c(2) <= g(1) or 
				 (p(1) and g(0)) or 
				 (p(1) and p(0) and cin);
				 
		c(3) <= g(2) or 
				 (p(2) and g(1)) or 
				 (p(2) and p(1) and g(0)) or 
				 (p(2) and p(1) and p(0) and cin);
				  
		cout <= g(3) or 
				 (p(3) and g(2)) or 
				 (p(3) and p(2) and g(1)) or 
				 (p(3) and p(2) and p(1) and g(0)) or 
				 (p(3) and p(2) and p(1) and p(0) and cin); 
	
	---computation of sum
	sum <= p xor c;
	
end architecture;