Carry Lookahead 16 bits
Ir para navegação
Ir para pesquisar
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
--Book: Eletronica digital moderna e VHDL/490 - Pelo autor
-- Carry lookahead com 16 bits
--
architecture adder_carry_lookahead_16 of adder is
signal carry: std_logic_vector(n/16 downto 0);
component carry_lookahead_adder_16 is
port( a,b : in std_logic_vector(15 downto 0);
cin: in std_logic;
cout: out std_logic;
sum: out std_logic_vector(15 downto 0));
end component;
begin
carry(0) <= cin;
gen_adder: for i in 1 to n/16 generate
adder: carry_lookahead_adder_16
port map(
a => a(16*i-1 downto 16*i-16),
b => b(16*i-1 downto 16*i-16),
cin => carry(i-1),
sum => sum(16*i-1 downto 16*i-16),
cout => carry(i)
);
end generate;
end architecture;