Códigos VHDL para uso nas Aulas

Descrever usando lógica discreta um decodificador de BCD para 7 segmentos.

entity Dec_7seg is
	port
	(
		eA,eB,eC,eD	: in  bit;
		a,b,c,d,e,f,g	: out bit
	);
end Dec_7seg;

architecture discret_logic of Dec_7seg is


begin
a <= (NOT eD AND NOT eC AND NOT eB AND eA) OR  
		(NOT eD AND eC AND NOT eB AND NOT eA);
b <= 
c <=
d <=
e <=
f <=
g <=

end discret_logic;