Códigos VHDL para uso nas Aulas

entity Dec_7seg is
	port
	(
		eA,eB,eC,eD	: in  bit;
		a,b,c,d,e,f,g	: out bit
	);
end Dec_7seg;

architecture discret_logic of Dec_7seg is


begin
a <= (NOT eD AND NOT eC AND NOT eB AND eA) OR  
		(NOT eD AND eC AND NOT eB AND NOT eA);
end discret_logic;