Mudanças entre as edições de "Códigos VHDL para uso nas Aulas"

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end discret_logic;
 
end discret_logic;
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</syntaxhighlight>
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<code>
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vcom -93 -work work {/home/moecke/ano2012-1/7-SEGv1/Dec_7seg.vhd}
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vsim work.dec_7seg
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add wave \
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{sim:/dec_7seg/ed } \
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{sim:/dec_7seg/ec } \
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{sim:/dec_7seg/eb } \
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{sim:/dec_7seg/ea } \
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{sim:/dec_7seg/g } \
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{sim:/dec_7seg/f } \
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{sim:/dec_7seg/e } \
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{sim:/dec_7seg/d } \
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{sim:/dec_7seg/c } \
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{sim:/dec_7seg/b } \
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{sim:/dec_7seg/a }
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 +
force -freeze sim:/dec_7seg/ea 0 0
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force -freeze sim:/dec_7seg/eb 0 0
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force -freeze sim:/dec_7seg/ec 0 0
 +
force -freeze sim:/dec_7seg/ed 0 0
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# numero 0
 +
run
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force -freeze sim:/dec_7seg/ea 1 0
 +
force -freeze sim:/dec_7seg/eb 0 0
 +
force -freeze sim:/dec_7seg/ec 0 0
 +
force -freeze sim:/dec_7seg/ed 0 0
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# numero 1
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run
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force -freeze sim:/dec_7seg/ea 0 0
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force -freeze sim:/dec_7seg/eb 1 0
 +
force -freeze sim:/dec_7seg/ec 0 0
 +
force -freeze sim:/dec_7seg/ed 0 0
 +
# numero 2
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run
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force -freeze sim:/dec_7seg/ea 1 0
 +
force -freeze sim:/dec_7seg/eb 1 0
 +
force -freeze sim:/dec_7seg/ec 0 0
 +
force -freeze sim:/dec_7seg/ed 0 0
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# numero 3
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run
 +
# complete até 9
 
</syntaxhighlight>
 
</syntaxhighlight>

Edição das 17h20min de 13 de março de 2012

Descrever usando lógica discreta um decodificador de BCD para 7 segmentos. Dec 7seg.png

Código

entity Dec_7seg is
	port
	(
		eA,eB,eC,eD	: in  bit;
		a,b,c,d,e,f,g	: out bit
	);
end Dec_7seg;

architecture discret_logic of Dec_7seg is


begin
--lógica que implementa o segmento a de um display (0,1,2,3,4,5,6,7,8,9), sem minimização.
-- 0 -> aceso (ON),  1 -> apagado (OFF)

a <= (NOT eD AND NOT eC AND NOT eB AND eA) OR  
		(NOT eD AND eC AND NOT eB AND NOT eA);
--implemente a lógica dos demais segmentos do display (0,1,2,3,4,5,6,7,8,9), sem minimização.
b <= (NOT eD AND eC AND NOT eB AND eA) OR  
		(NOT eD AND eC AND eB AND NOT eA);
c <= (NOT eD AND NOT eC AND  eB AND eA);
d <= (NOT eD AND NOT eC AND NOT eB AND eA) OR  
		(NOT eD AND eC AND NOT eB AND NOT eA) OR
                (NOT eD AND eC AND eB AND  eA);
e <= (NOT eD AND NOT eC AND NOT eB AND  eA) OR  
		(NOT eD AND NOT eC AND  eB AND  eA) OR
                (NOT eD AND eC AND NOT eB AND NOT eA) OR  
		(NOT eD AND eC AND NOT eB AND eA) OR
                (NOT eD AND  eC AND  eB AND  eA) OR  
		( eD AND NOT eC AND NOT eB AND eA);
f <=            (NOT eD AND NOT eC AND NOT eB AND eA) OR  
		(NOT eD AND NOT eC AND  eB AND NOT eA) OR
                (NOT eD AND NOT eC AND eB AND  eA) OR  
		(NOT eD AND  eC AND  eB AND  eA);
g <=            (NOT eD AND NOT eC AND NOT eB AND NOT eA) OR  
		(NOT eD AND NOT eC AND NOT eB AND  eA) OR
                (NOT eD AND  eC AND  eB AND  eA);

end discret_logic;

vcom -93 -work work {/home/moecke/ano2012-1/7-SEGv1/Dec_7seg.vhd} vsim work.dec_7seg add wave \ {sim:/dec_7seg/ed } \ {sim:/dec_7seg/ec } \ {sim:/dec_7seg/eb } \ {sim:/dec_7seg/ea } \ {sim:/dec_7seg/g } \ {sim:/dec_7seg/f } \ {sim:/dec_7seg/e } \ {sim:/dec_7seg/d } \ {sim:/dec_7seg/c } \ {sim:/dec_7seg/b } \ {sim:/dec_7seg/a }

force -freeze sim:/dec_7seg/ea 0 0 force -freeze sim:/dec_7seg/eb 0 0 force -freeze sim:/dec_7seg/ec 0 0 force -freeze sim:/dec_7seg/ed 0 0

  1. numero 0

run force -freeze sim:/dec_7seg/ea 1 0 force -freeze sim:/dec_7seg/eb 0 0 force -freeze sim:/dec_7seg/ec 0 0 force -freeze sim:/dec_7seg/ed 0 0

  1. numero 1

run force -freeze sim:/dec_7seg/ea 0 0 force -freeze sim:/dec_7seg/eb 1 0 force -freeze sim:/dec_7seg/ec 0 0 force -freeze sim:/dec_7seg/ed 0 0

  1. numero 2

run force -freeze sim:/dec_7seg/ea 1 0 force -freeze sim:/dec_7seg/eb 1 0 force -freeze sim:/dec_7seg/ec 0 0 force -freeze sim:/dec_7seg/ed 0 0

  1. numero 3

run

  1. complete até 9

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