Códigos VHDL para uso nas Aulas
Decodificador de BCD para 7 segementos
Descrever usando lógica discreta um decodificador de BCD para 7 segmentos. A interface externa do decodificador deve ter as entradas eA, eB, eC e eD, e as saídas os sete segmentos a, b, c, d, e, f, g. Neste exemplo esta sendo considerada a logica negativa onde o segmento acesso corresponde a 0 e apagado -> 1. Entradas só são consideradas válidas de 0 (0000) até 9 (1001), ou seja o circuito não precisa tratar as entradas entre A (1010) e F(1111).
Tabela Verdade
Código VHDL (lógica discreta)
entity Dec_7seg is
port
(
eA,eB,eC,eD : in bit;
a,b,c,d,e,f,g : out bit
);
end Dec_7seg;
architecture discret_logic of Dec_7seg is
begin
--lógica que implementa o segmento a de um display (0,1,2,3,4,5,6,7,8,9), sem minimização.
-- 0 -> aceso (ON), 1 -> apagado (OFF)
a <= (NOT eD AND NOT eC AND NOT eB AND eA) OR
(NOT eD AND eC AND NOT eB AND NOT eA);
--implemente a lógica dos demais segmentos do display (0,1,2,3,4,5,6,7,8,9), sem minimização.
b <= (NOT eD AND eC AND NOT eB AND eA) OR
(NOT eD AND eC AND eB AND NOT eA);
c <= (NOT eD AND NOT eC AND eB AND eA);
d <= (NOT eD AND NOT eC AND NOT eB AND eA) OR
(NOT eD AND eC AND NOT eB AND NOT eA) OR
(NOT eD AND eC AND eB AND eA);
e <= (NOT eD AND NOT eC AND NOT eB AND eA) OR
(NOT eD AND NOT eC AND eB AND eA) OR
(NOT eD AND eC AND NOT eB AND NOT eA) OR
(NOT eD AND eC AND NOT eB AND eA) OR
(NOT eD AND eC AND eB AND eA) OR
( eD AND NOT eC AND NOT eB AND eA);
f <= (NOT eD AND NOT eC AND NOT eB AND eA) OR
(NOT eD AND NOT eC AND eB AND NOT eA) OR
(NOT eD AND NOT eC AND eB AND eA) OR
(NOT eD AND eC AND eB AND eA);
g <= (NOT eD AND NOT eC AND NOT eB AND NOT eA) OR
(NOT eD AND NOT eC AND NOT eB AND eA) OR
(NOT eD AND eC AND eB AND eA);
end discret_logic;
Código TCL para teste do Hardware
vcom -93 -work work {/home/moecke/ano2012-1/7-SEGv1/Dec_7seg.vhd}
vsim work.dec_7seg
add wave \
{sim:/dec_7seg/ed } \
{sim:/dec_7seg/ec } \
{sim:/dec_7seg/eb } \
{sim:/dec_7seg/ea } \
{sim:/dec_7seg/g } \
{sim:/dec_7seg/f } \
{sim:/dec_7seg/e } \
{sim:/dec_7seg/d } \
{sim:/dec_7seg/c } \
{sim:/dec_7seg/b } \
{sim:/dec_7seg/a }
force -freeze sim:/dec_7seg/ea 0 0
force -freeze sim:/dec_7seg/eb 0 0
force -freeze sim:/dec_7seg/ec 0 0
force -freeze sim:/dec_7seg/ed 0 0
- numero 0
run
force -freeze sim:/dec_7seg/ea 1 0
force -freeze sim:/dec_7seg/eb 0 0
force -freeze sim:/dec_7seg/ec 0 0
force -freeze sim:/dec_7seg/ed 0 0
- numero 1
run
force -freeze sim:/dec_7seg/ea 0 0
force -freeze sim:/dec_7seg/eb 1 0
force -freeze sim:/dec_7seg/ec 0 0
force -freeze sim:/dec_7seg/ed 0 0
- numero 2
run
force -freeze sim:/dec_7seg/ea 1 0
force -freeze sim:/dec_7seg/eb 1 0
force -freeze sim:/dec_7seg/ec 0 0
force -freeze sim:/dec_7seg/ed 0 0
- numero 3
run
- complete até 9
</syntaxhighlight>
Circuito RTL a ser testado