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{{collapse top| bg=lightgreen | expandir=true |Semestre 2015-2 - Prof. Arliones Hoeller}} | {{collapse top| bg=lightgreen | expandir=true |Semestre 2015-2 - Prof. Arliones Hoeller}} | ||
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{{Cl|1 |2/10 | 2 | Introduction to Embedded Systems: History Overview and Fundamental Concepts. | Lab. Redes I}} | {{Cl|1 |2/10 | 2 | Introduction to Embedded Systems: History Overview and Fundamental Concepts. | Lab. Redes I}} | ||
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{{Cl|7 |23/10 | 2,4 | I/O Basics: Interrupt Handling. | Lab. Redes I}} | {{Cl|7 |23/10 | 2,4 | I/O Basics: Interrupt Handling. | Lab. Redes I}} | ||
{{Cl|8 |27/10 | 2 | I/O Basics: Programmed I/O and DMA. | Lab. Redes I}} | {{Cl|8 |27/10 | 2 | I/O Basics: Programmed I/O and DMA. | Lab. Redes I}} | ||
− | {{Cl|9 | | + | {{Cl|9 |6/11 | 2,4 | Timers and Counters. | Lab. Redes I}} |
− | {{Cl|10 | | + | {{Cl|10 |10/11 | 2 | Watchdog and Real-Time Clock. | Lab. Redes I}} |
− | {{Cl|11 | | + | {{Cl|11 |13/11 | 2,4 | Interfacing to the Analog World: ADC and Sensors. | Lab. Redes I}} |
− | {{Cl|12 | | + | {{Cl|12 |17/11 | 2 | Interfacing to the Analog World: DAC and Actuators. | Lab. Redes I}} |
− | {{Cl|13 | | + | {{Cl|13 |20/11 | 2,4 | Introduction to Real-Time Systems: Fundamentals and Periodic Scheduling. | Lab. Redes I}} |
− | {{Cl|14 | | + | {{Cl|14 |24/11 | 2 | Introduction to Real-Time Systems: Aperiodic Scheduling and Priority Inversion. | Lab. Redes I}} |
− | {{Cl|15 | | + | {{Cl|15 |27/11 | 2,4 | Embedded Real-Time Operating Systems | Lab. Redes I}} |
− | {{Cl|16 | | + | {{Cl|16 |1/12 | 2 | Networking: Field Buses and CAN. | Lab. Redes I}} |
− | {{Cl|17 | | + | {{Cl|17 |4/12 | 2,4 | Networking: Wireless Control Networks and IEEE 802.15.4. | Lab. Redes I}} |
− | {{Cl|18 | | + | {{Cl|18 |8/12 | 2 | Networking: Ethernet. | Lab. Redes I}} |
− | {{Cl|19 | | + | {{Cl|19 |11/12 | 2,4 | Final Project: System Vision Document | Lab. Redes I}} |
− | {{Cl|20 | | + | {{Cl|20 |15/12 | 2 | Final Project: System Vision Document – Presentation | Lab. Redes I}} |
− | {{Cl|21 | | + | {{Cl|21 |18/12 | 2,4 | Final Project: Specification and Analysis | Lab Redes I}} |
− | {{Cl|22 | | + | {{Cl|22 |22/12 | 2 | Final Project: Specification and Analysis – Checkpoint | Lab Redes I}} |
− | {{Cl|23 | | + | {{Cl|23 |2/2 | 2 | Final Project: Specification and Analysis – Presentation | Lab Redes I}} |
− | {{Cl|24 | | + | {{Cl|24 |5/2 | 2 | Final Project: Implementation | Lab Redes I}} |
− | {{Cl|25 | | + | {{Cl|25 |12/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}} |
− | {{Cl|26 | | + | {{Cl|26 |16/2 | 2 | Final Project: Implementation | Lab Redes I}} |
− | {{Cl|27 | | + | {{Cl|27 |19/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}} |
− | {{Cl|28 | | + | {{Cl|28 |23/2 | 2 | Final Project: Implementation | Lab Redes I}} |
− | {{Cl|29 | | + | {{Cl|29 |26/2 | 2 | Final Project: Implementation – Checkpoint | Lab Redes I}} |
− | {{Cl|30 | | + | {{Cl|30 |1/3 | 2 | Final Project: Implementation | Lab Redes I}} |
− | {{Cl|31 | | + | {{Cl|31 |4/3 | 2 | Final Project: Implementation – Presentation | Lab Redes I}} |
− | {{Cl|32 | | + | {{Cl|32 |8/3 | 2 | Final Project: Integration | Lab Redes I}} |
− | {{Cl|33 | | + | {{Cl|33 |11/3 | 2 | Final Project: Integration – Checkpoint | Lab Redes I}} |
− | {{Cl|34 | + | {{Cl|34 |15/3 | 2 | Final Project: Integration | Lab Redes I}} |
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Edição das 13h51min de 29 de outubro de 2015
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