Mudanças entre as edições de "Uso de Logic Lock para definir a área a ser ocupada pelo circuito"
Ir para navegação
Ir para pesquisar
Linha 3: | Linha 3: | ||
=Referências externas= | =Referências externas= | ||
− | *[https://www. | + | *[https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qts_qii52009.pdf LogicLock Design Methodology] |
*[http://www.unimasr.net/ums/upload/files/2012/Apr/UniMasr.com_7383dccbcdfd7983a60b1444678949c6.pdf Using the LogicLock Methodology in the Quartus II Design Software] - Application Note 161 | *[http://www.unimasr.net/ums/upload/files/2012/Apr/UniMasr.com_7383dccbcdfd7983a60b1444678949c6.pdf Using the LogicLock Methodology in the Quartus II Design Software] - Application Note 161 | ||
− | *[https://www. | + | *[https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/an/an297.pdf Optimizing FPGA Performance Using the Quartus II Software] - Application Note 297 |
*[http://www.alterawiki.com/uploads/6/61/Tips_for_IncrementalCompilation_LogicLock.pdf Tips for Incremental Compilation And LogicLock] | *[http://www.alterawiki.com/uploads/6/61/Tips_for_IncrementalCompilation_LogicLock.pdf Tips for Incremental Compilation And LogicLock] | ||
*[https://engineering.purdue.edu/ISLWiki/pub/Variations/FpgaFlow/incrementalcompilation.pdf Quartus II Incremental Compilation for Hierarchical and Team-Based Design] | *[https://engineering.purdue.edu/ISLWiki/pub/Variations/FpgaFlow/incrementalcompilation.pdf Quartus II Incremental Compilation for Hierarchical and Team-Based Design] |
Edição das 23h47min de 28 de fevereiro de 2019
A metodologia de LogicLock auxilia no projeto e otimização de dispositivos lógicos programáveis, possibilitando o controle do usuário sobre o reuso de projetos e módulos, e a realização de projeto hierárquico e incremental. O documento LogicLock Methodology, entre outras características descreve as propriedades das regiões de LogicLock (Location = Floating | Locked; Size = Auto | Fixed), e características gerais do projeto modular, hierárquico, incremental, em equipes, e o reuso de projetos. O procedimento a ser seguido para o uso dos LogicLock é descrito em Creating and Manipulating LogicLock Regions
Referências externas
- LogicLock Design Methodology
- Using the LogicLock Methodology in the Quartus II Design Software - Application Note 161
- Optimizing FPGA Performance Using the Quartus II Software - Application Note 297
- Tips for Incremental Compilation And LogicLock
- Quartus II Incremental Compilation for Hierarchical and Team-Based Design