Timing Closure - Quartus

About Timing Closure

One of the greatest and most frustrating FPGA design challenges is closing timing. It is very common to find, after performing a complete timing analysis on an FPGA design, that one or more timing reports indicate a timing failure. How can this be corrected? There are many techniques, including thoroughly analyzing the design for common timing failures, adjusting settings and assignments according to tool recommendations, selecting the correct clock resources, and adjusting HDL code for optimal performance. There are many different tools and reports within the Intel® Quartus® Prime Pro Development Software that will help you get the best performance out of your design and get to timing closure faster.

More Information

• Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer
• AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition
• AN 584: Timing Closure Methodology for Advanced FPGA Design
• Best Design Practices for Timing Closure
• Using Design Space Explorer
• Creating High-Performance Designs in Intel Stratix 10 FPGAs